SN65LVCP23
- High Speed 2x2 LVPECL Crosspoint Switch
- LVDS Crosspoint Switch Available in SN65LVCP22
- 50 ps (Typ), of Peak-to-Peak Jitter With PRBS = 223- 1 Pattern
- Output (Channel-to-Channel) Skew Is 10 ps (Typ), 50 ps (Max)
- Configurable as 2:1 Mux, 1:2 Demux, Repeater or 1:2 Signal Splitter
- Inputs Accept LVDS, LVPECL, and CML Signals
- Fast Switch Time of 1.7 ns (Typ)
- Fast Propagation Delay of 0.75 ns (Typ)
- 16 Lead SOIC and TSSOP Packages
- Operating Temperature: -40°C to 85°C
- APPLICATIONS
- Gigabit Ethernet Redundant Transmission Paths
- Gigabit Interface Converters (GBICs)
- Fibre Channel Redundant Transmission Paths
- HDTV Video Routing
- Base Stations
- Protection Switching for Serial Backplanes
- Network Switches/Routers
- Optical Networking Line Cards/Switches
- Clock Distribution
The SN65LVCP23 is a 2x2 LVPECL crosspoint switch. The dual channels incorporate wide common-mode (0 V to 4 V) receivers, allowing for the receipt of LVDS, LVPECL, and CML signals. The dual outputs are LVPECL drivers to provide high-speed operation. The SN65LVCP23 provides a single device supporting 2:2 buffering (repeating), 1:2 splitting, 2:1 multiplexing, 2x2 switching, and LVDS/CML to LVPECL level translation on each channel. The flexible operation of the SN65LVCP23 provides a single device to support the redundant serial bus transmission needs (working and protection switching cards) of fault-tolerant switch systems found in optical networking, wireless infrastructure, and data communications systems. TI offers an additional gigabit repeater/translator in the SN65LVDS101.
The SN65LVCP23 uses a fully differential data path to ensure low-noise generation, fast switching times, low pulse width distortion, and low jitter. Output channel-to-channel skew is less than 10 ps (typ) and 50 ps (max) to ensure accurate alignment of outputs in all applications. Both SOIC and TSSOP package options are available.
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技術文件
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | 2x2 LVPECL Crosspoint Switch datasheet (Rev. E) | 2006年 5月 10日 |
設計與開發
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
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