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Serdes (Serializer/Deserializer) Receiver

Inventory: 3,505

Download data sheet for SN65LVDS96
  |   View additional information for SN65LVDS96

Same as: SN65LVDS96DGGG4  This part number is identical to the part number listed above. You can only order quantities of the part number listed above.

Packaging information

Package | Pins TSSOP (DGG) | 48
Operating temperature range (°C)
Package qty | Carrier: 40 | TUBE
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Quality information

RoHS Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-2-260C-1 YEAR
Material content View
DPPM / MTBF / Fit rate View
Qualification summary View
Ongoing reliability monitoring View
Device marking View


  • 3:21 Data Channel Compression at up to1.428 Gigabits/s Throughput
  • Suited for Point-to-Point Subsystem Communication With Very Low EMI
  • 3 Data Channels and Clock Low-Voltage Differential Channels in and 21 Data and Clock Low-Voltage TTL Channels Out
  • Operates From a Single 3.3-V Supply and 250 mW (Typ)
  • 5-V Tolerant SHTDN Input
  • Rising Clock Edge Triggered Outputs
  • Bus Pins Tolerate 4-kV HBM ESD
  • Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
  • Consumes <1 mW When Disabled
  • Wide Phase-Lock Input Frequency Range 20 MHz to 68 MHz
  • No External Components Required for PLL
  • Inputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • Industrial Temperature Qualified TA = -40°C to 85°C
  • Replacement for the DS90CR216


The SN65LVDS96 LVDS serdes (serializer/deserializer) receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such asthe SN65LVDS95, over four balanced-pair conductors and expansion to 21 bits of single-ended LVTTL synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times the LVDS input clock (CLKIN). The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN65LVDS96 presents valid data on the rising edge of the output clock (CLKOUT).

The SN65LVDS96 requires only four line termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

The SN65LVDS96 is characterized for operation over ambient air temperatures of -40°C to 85°C.

Qty Price
1-99 $8.00
100-249 $6.52
250-999 $5.13
1,000+ $4.35