CDCLVD1213 Low Jitter, 1:4 Universal-to-LVDS Buffer with Selectable Output Divider | TI.com

CDCLVD1213
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
Low Jitter, 1:4 Universal-to-LVDS Buffer with Selectable Output Divider

 

Recommended alternative parts

  • LMK00301  - The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device.   Ultra low additive jitter,1:10 Universal Differential Buffer that can support LVDS

Description

The CDCLVD1213 clock buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution. The input can either be LVDS, LVPECL, or CML.

The CDCLVD1213 contains a high performance divider for one output (QD) which can divide the input clock signal by a factor of 1, 2, or 4.

The CDCLVD1213 is specifically designed for driving 50-Ω transmission lines. The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1213 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.

Features

  • 1:4 Differential Buffer
  • Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
  • Low Output Skew of 20 ps (Maximum)
  • Selectable Divider Ratio 1, /2, /4
  • Universal Input Accepts LVDS, LVPECL, and CML
  • 4 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency: Up to 800 MHz
  • Device Power Supply: 2.375 V to 2.625 V
  • Industrial Temperature Range: –40°C to 85°C
  • Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
  • ESD Protection Exceeds 3-kV HBM, 1-kV CDM
  • APPLICATIONS
    • Telecommunications and Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General-Purpose Clocking

Parametrics

Compare all products in Clock buffers Email Download to Excel
Part number Order Function Additive RMS jitter (Typ) (fs) Output frequency (Max) (MHz) Number of outputs VCC out (V) VCC core (V) Output skew (ps) Features Operating temperature range (C) Rating Output type Package Group Package size: mm2:W x L (PKG) Input type
CDCLVD1213 Order now Differential     171     800     4     2.5     2.5     20     1:4 fanout
Selectable divider
Universal inputs    
-40 to 85     Catalog     LVDS     VQFN | 16     16VQFN: 9 mm2: 3 x 3 (VQFN | 16)     LVCMOS
LVDS
LVPECL    
CDCLVD110A Order now Differential     111     1100     10     2.5     2.5       1:10 fanout
Individual output enable control    
-40 to 85     Catalog     LVDS     LQFP | 32
VQFN | 32    
32LQFP: 49 mm2: 7 x 7 (LQFP | 32)
32VQFN: 25 mm2: 5 x 5 (VQFN | 32)    
LVDS    
CDCLVD1204 Order now Differential     171     800     4     2.5     2.5     20     2:4 fanout
Universal inputs    
-40 to 85     Catalog     LVDS     VQFN | 16     16VQFN: 9 mm2: 3 x 3 (VQFN | 16)     LVCMOS
LVDS
LVPECL    
CDCLVD1208 Order now Differential     171     800     8     2.5     2.5     45     2:8 fanout
Universal inputs    
-40 to 85     Catalog     LVDS     VQFN | 28     28VQFN: 25 mm2: 5 x 5 (VQFN | 28)     LVCMOS
LVDS
LVPECL    
CDCLVD1212 Order now Differential     171     800     12     2.5     2.5     35     2:12 fanout
Universal inputs    
-40 to 85     Catalog     LVDS     VQFN | 40     40VQFN: 36 mm2: 6 x 6 (VQFN | 40)     LVCMOS
LVDS
LVPECL    
CDCLVD1216 Order now Differential     171     800     16     2.5     2.5     55     2:16 fanout
Universal inputs    
-40 to 85     Catalog     LVDS     VQFN | 48     48VQFN: 49 mm2: 7 x 7 (VQFN | 48)     LVCMOS
LVDS
LVPECL    
CDCLVD2102 Order now Differential     171     800     4     2.5     2.5