CDCLVP1212
- 2:12 Differential Buffer
- Selectable Clock Inputs Through Control Terminal
- Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL - 12 LVPECL Outputs
- Maximum Clock Frequency: 2 GHz
- Maximum Core Current Consumption: 88 mA
- Very Low Additive Jitter: <100 fs, rms in 10-kHz to
20-MHz Offset Range:- 57 fs, rms (typ) @ 122.88 MHz
- 48 fs, rms (typ) @ 156.25 MHz
- 30 fs, rms (typ) @ 312.5 MHz
- 2.375-V to 3.6-V Device Power Supply
- Maximum Propagation Delay: 550 ps
- Maximum Output Skew: 25 ps
- LVPECL Reference Voltage, VAC_REF, Available
for Capacitive-Coupled Inputs - Industrial Temperature Range: –40°C to 85°C
- ESD Protection Exceeds 2 kV (HBM)
- Supports 105°C PCB Temperature (Measured
with a Thermal Pad) - Available in 6-mm × 6-mm QFN-40 (RHA) Package
The CDCLVP1212 is a highly versatile, low additive jitter buffer that can generate 12 copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1212 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 25 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1212 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 12 pairs of differential LVPECL clock outputs (OUT0, OUT11) with minimum skew for clock distribution. The CDCLVP1212 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1212 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1212 is packaged in a small 40-terminal, 6-mm × 6-mm QFN package and is characterized for operation from 40°C to 85°C.
Similar products you might be interested in
Similar functionality to the compared device
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | CDCLVP1212 LVPECL Output, High-Performance Clock Buffer datasheet (Rev. E) | PDF | HTML | 02 Dec 2015 |
Application note | Clocking Design Guidelines: Unused Pins | 19 Nov 2015 | ||
EVM User's guide | Low Additive Phase Noise Clock Buffer Evaluation Board | 25 Aug 2009 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
CLOCK-TREE-ARCHITECT — Clock tree architect programming software
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
Package | Pins | Download |
---|---|---|
VQFN (RHA) | 40 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
- Fab location
- Assembly location
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
Support & training
TI E2E™ forums with technical support from TI engineers
Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.
If you have questions about quality, packaging or ordering TI products, see TI support.