TI Triple rate SDI module for Xilinx XtremeDSP starter platform


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Texas Instruments in collaboration with Xilinx developed a triple-rate SDI and video clocking daughter card for the Xilinx Spartan-3A/3E development kits. The daughter card plugs directly into the Spartan development board through an EXP connector. The combined solution of the daughter card and the development kit provides broadcast video system designers a comprehensive platform for rapid evaluation and prototyping of new designs to reduce time to market.

The daughter card is also referred in the documents below by its internal TI part name SDXILEVK. The TI part name is used for reference only and cannot be used to order the part.

The 3G SDI SerDes evaluation system consists of:

SDXILEVK Hardware Platform


Xilinx Spartan-3A Host Development Board LED LED LED LED Power Supply Spartan-3A LP3878-ADJ LMH0340 LMH0341 LMH0344 DS25CP104A LMH1982 LMH1981


The SDXILEVK daughter card contains:

  • LMH0344 - Triple-rate SDI Adaptive Cable Equalizer
  • LMH0340 - Triple-rate SDI Serializer with integrated cable driver
  • LMH0341 - Triple-rate SDI deserializer with reclocked loop through
  • LMH1981 - Multi-Format Video Sync Separator
  • LMH1982 - Multi-Rate Video Clock Generator
  • DS25CP104A - 4x4 LVDS Crosspoint Switch
  • LP3878-ADJ - Low Noise LDO

The SDXILEVK supports a complete 3G-SDI signal path consisting of adaptive cable equalizer (LMH0344), deserializer with reclocked loop through (LMH0341) and serializer with integrated cable driver (LMH0340). A multi-rate sync separator (LMH1981) and clock generator (LMH1982) deliver ultra-low jitter reference clocks to the host FPGA. A 4x4 LVDS crosspoint switch (DS25CP104A) acts as a reference clock selector to choose between four separate clocking options:

  • Recovered clock from LMH0341 deserializer
  • Genlock from analog reference, LMH1981 sync separator and LMH1982 clock generator
  • Local clock generation from LMH1982 in free-run mode
  • External clock via SMA connector

These selectable reference clocks allow designers to compare system performance using different clocking sources. For example, one application may require genlock capability for synchronization while another one leverages the recovered clock from the SDI deserializer. Designers may compare system jitter performance of each clocking solution then make architectural decisions based on system requirements and constraints.

FPGA IP Description

A full set of FPGA firmware is available from TI as source code to enable quick system integration and faster time to market. This IP implements the SMPTE SDI framing and deframing protocols. A reference design using this IP is available for the Xilinx Spartan-3A/3E host development kits and is compatible with other Spartan-3A and Spartan-3E devices.

The IP architecture includes:

  • Triple rate SDI support with automatic rate detect
  • SMPTE scrambling, descrambling and framing
  • Audio embedding and de-embedding
  • Test pattern generation for development and validation
  • 20:5 output muxing and 5:20 input demuxing to support the 5-bit LVDS interface bus
  • SMBus management interface

By providing both the hardware and FPGA firmware, TI enables maximum flexibility to modify system design, quickly adapt to standard changes, add features, and reduce time-to-market. Competing solutions that integrate the protocol blocks locally in the discrete SerDes, constrain system designs to a minimal set of digital functions.



FPGA Source Triple-Rate 3G/HD/SD Audio Embed/De-Embed Gen Lock Clocking Verilog Source VHDL Source FPGA IP
Xilinx Spartan-3A/3E TI/Avnet Contact TI (see below)


Feature Benefit
Triple-Rate SDI Supports SD, HD and 3G-SDI (SMPTE 259M-C, 292M, 424M)
Four Clocking Options Compare SerDes jitter performance with multiple reference clocks
Verilog or VHDL Source Code Flexible SMPTE IP allows users to easily customize features and functions
Genlock Synchronize timing to analog house reference
Audio Embedding / De-embedding Support up to 8-channels of audio embed / de-embed
Serial Reclocked Loop Through Enables low-jitter input monitoring or daisy chaining
Two Triple-Rate SDI Outputs Support Dual-Link SMPTE
High Input Jitter Tolerance Receive, lock and deserialize noisy signals with accumulated jitter
Ultra-Low Output Alignment Jitter Transmit ultra-clean output signals well within SMPTE jitter specifications


The FPGA IP is available for download as a SRAM Object File (SOF) file. Texas Instruments provides synthesizable FPGA source code in both Verilog and VHDL formats. Please contact your local TI representative to obtain a login and password to the FPGA IP FTP site.

SDXILEVK Design Resources

Ordering Info

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TI Triple rate SDI module for Xilinx XtremeDSP starter platform


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Technical Documents
Design Files (2)
Title Abstract Type Size (KB) Date Views
PDF 493 05 Mar 2012 563
ZIP 57 05 Mar 2012 128
More Literature (1)
Title Abstract Type Size (KB) Date Views
PDF 50 05 Mar 2012 561

Software (1)

Name Part Number Software Type
Broadcast Video Support Code for LVDS Interface SDI SerDes  BROADCAST_VIDEO_SERDES_IP  Software Development Kits (SDK) 

TI Devices (7)

Part Number Name Product Family
DS25CP104A  3.125 Gbps 4x4 LVDS Crosspoint Switch with Tx Pre-Emphasis & Rx Equalization  LVDS/M-LVDS/ECL/CML 
LMH0340  3Gbps, HD, SD, DVB-ASI SDI Serializer and Driver with LVDS Interface  Video: Broadcast & Professional 
LMH0341  3Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface  Video: Broadcast & Professional 
LMH0344  3 Gbps HD/SD SDI Adaptive Cable Equalizer  Video: Broadcast & Professional 
LMH1981  Multi-Format Video Sync Separator  Video: Broadcast & Professional 
LMH1982  Multi-Rate Video Clock Generator with Genlock  Video: Broadcast & Professional 
LP3878-ADJ  Micropower 800mA Low Noise 'Ceramic Stable' Adjustable Voltage Regulator for 1V to 5V App.  Linear Regulator (LDO) 

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