The ADS1262 and ADS1263 are precision 32-bit, delta-sigma (ΔΣ) ADCs with an integrated analog front end (AFE) to simplify connection to sensors. A 32-bit ADC (ADC1) provides output data rates from 2.5 SPS to 38400 SPS for flexibility in resolution and data rates over a wide range of applications. The ADC low noise and low drift architecture make these devices suitable for precise digitization of low-level transducers, such as load cell bridges and temperature sensors. The ADS1263 includes an auxiliary 24-bit delta-sigma ADC (ADC2).
The ADS1262 and the ADS1263 incorporate several functions that provide increased utility. The key integrated functions include:
As shown in the Section 9.2, these devices feature 11 analog inputs that are configurable as either ten single-ended inputs, five differential inputs, or any combination, to either ADC1 or ADC2. Many of the analog inputs are multifunction as programmed by the user. The analog inputs can be programmed to the following extended functions:
Following the input multiplexer (mux), ADC1 features a high-impedance, CMOS, programmable gain amplifier (PGA). The PGA provides very low voltage and current noise, enabling direct connection to low-level transducers, and in many cases, eliminating the need for an external amplifier. The PGA gain is programmable from 1 V/V to 32 V/V in binary steps. The PGA can be bypassed to allow the input range to extend below ground. The PGA has voltage overrange monitors to improve the integrity of the conversion result. The PGA overrange alarm is latched during the conversion phase and appended to the conversion data. The programmable sensor bias uses a test current to help detect a failed sensor or sensor connection.
An inherently stable delta-sigma modulator measures the ratio of the input voltage to the reference voltage to provide the ADC result. The ADC operates with the internal 2.5-V reference, or with up to three external reference inputs. The external reference inputs are continuously monitored for low (or missing) voltage. The reference alarm status is latched during the conversion phase and appended to the conversion data. The REFOUT pin is the buffered 2.5-V internal voltage reference output.
Dual excitation current sources (IDAC) provide bias to resistance sensors (such as 3-wire RTD). The ADC integrates several system monitors for readback, such as temperature sensor and supply monitor. The ADC features an internal test signal voltage (TDAC) that is used to verify the ADC operation across all gains. The TDAC has two outputs to provide test voltages for single-ended and differential input configurations. Eight GPIO ports are available on the analog input pins.
The digital filter provides two functional modes, sinc and FIR, allowing optimization of settling time and line-cycle rejection. The sinx/x (sinc) filter is programmable to sinc orders one through four to tradeoff filter settling time and 50-Hz and 60-Hz line-cycle rejection. The finite impulse response (FIR) filter mode provides single-cycle settled data with 50-Hz and 60-Hz line cycle rejection at data rates up to 20 SPS.
The ADS1263 includes an auxiliary 24-bit delta-sigma ADC (ADC2) featuring buffered PGA inputs, gains from 1 V/V to 128 V/V, and data rates up to 800 SPS. All analog inputs and reference inputs are available to ADC2. ADC2 can be used to provide redundant measurements or system measurements such as sensor temperature compensation and thermocouple cold junction compensation (CJC). The ADS1263 is pin and functionally compatible to the ADS1262.
The SPI™-compatible serial interface is used to read the conversion data and also to configure and control the ADC. The serial interface consists of four signals: CS, SCLK, DIN and DOUT/DRDY. The conversion data are provided with a CRC code for improved data integrity. The dual function DOUT/DRDY output indicates when conversion data are ready and also provides the data output. The serial interface can be implemented with as little as three connections by tying CS low.
The ADC has three clock options: internal oscillator, external crystal, and external clock. The ADC detects the clock mode automatically. The nominal clock frequency is 7.3728 MHz.
ADC conversions are started by a control pin or by commands. The ADC can be programmed to free-run mode or perform one-shot conversions. The DRDY and DOUT/DRDY pins are driven low when the conversion data are ready. The RESET/PWDN digital input resets the ADC when momentarily pulsed low, and when held low, enables the ADC power-down mode.
The ADC operates with bipolar (± 2.5 V) supplies, or with a single 5-V supply. For single-supply operation, use the internal level-shift voltage to level-shift isolated (floating) sensors. The digital power-supply range is 2.7 V to 5.25 V. The BYPASS pin is the subregulator output (2 V) that is used for internal digital supply.