ADC2 features a low-drift, low-noise CMOS PGA. The ADC2 PGA is bypassed for gains = 1, 2 and 4. Therefore, for these gains the input signal is connected directly to the buffered modulator input.
The full-scale voltage range of ADC2 is determined by the reference voltage and gain. Table 9-9 shows the ADC2 full-scale voltage range versus gain using reference voltage = 2.5 V. The full-scale voltage range scales with the reference voltage and is increased or decreased by changing the reference voltage.
OF ADC2CFG REGISTER
|GAIN (V/V)||FULL-SCALE INPUT RANGE|
As with many amplifiers, do not exceed the PGA absolute input voltage requirement. For gains ≥ 8 (PGA active), the absolute input voltage is limited by the PGA output voltage swing range. The specified minimum and maximum absolute input voltages (VINP2 and VINN2) depend on the PGA gain, the input differential voltage (VIN2), and the tolerance of the analog power supply voltages (VAVDD, VAVSS). If using ADC2 in an overall gain ≥ 8, the absolute positive and negative input voltage must be within the specified range, as shown in Equation 15:
For gains 1, 2, or 4, the ADC2 absolute input voltage range extends beyond the VAVDD and VAVSS supply voltages, allowing voltage inputs at or below ground. The absolute input voltage range corresponding to gains 1, 2 and 4 is shown in Equation 16: