Power down the ADC by holding the RESET/PWDN pin low. To reset the ADC without engaging power-down mode, pulse the pin low for less than 65536 clock cycles. In power-down mode, the ADC (including the internal reference) is shutdown. The internal low-dropout regulator (LDO) output to the BYPASS pin remains on, typically drawing 25-µA idle current from the DVDD power supply. To exit power-down mode, take the RESET/PWDN pin high.
While in power-down mode, the ADC digital outputs remain driven and the analog inputs and reference inputs are high impedance. Maintain the digital inputs at VIH or VIL levels (do not float the digital inputs). When power-down mode is exited, the ADC resets, resulting in the registers resetting to default values. Wait the required 65536 fCLK cycles (9 ms) before first communication to the ADC. Make sure to allow time for the internal reference to settle before starting the first conversion.