ADC1 contains an integrated a PGA absolute output-voltage monitor. If the absolute level of the PGA positive or negative output exceeds VAVDD – 0.2 V, the PGA high alarm triggers (PGAH_ALM). If the absolute level of the PGA positive or negative output voltage is less than VAVSS + 0.2 V, the PGA low alarm triggers (PGAL_ALM). The alarms are set in the status byte corresponding to the conversion cycle when the alarms occurred. For the next conversion cycle, the alarms reset. If the magnitude of PGA output voltages remains within the range (VAVDD – 0.2 V and VAVSS + 0.2 V), the alarms remain reset. The PGA absolute output-voltage monitor block diagram is shown in Figure 9-10.
Figure 9-11 shows an example of the PGA absolute output-voltage monitor overrange event.