ADC1 incorporates a differential PGA output voltage monitor. This voltage monitor triggers an alarm when the magnitude of the differential PGA output voltage is more positive than +105% or more negative than –105% of full scale, but only during a conversion cycle. The alarm event, corresponding to the conversion cycle when the alarm occurred, is set in the status byte (PGAD_ALM). For the next conversion, the alarm resets. If the magnitude of differential output voltage is within the range of ±105% of full-scale range, the alarm remains reset. The PGA differential monitor block diagram is shown in Figure 9-8.
Figure 9-9 shows an example of the differential overrange monitor event.