SLUSDV2A May   2020  ā€“ May 2021 BQ25798


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Device Power-On-Reset
      2. 8.3.2  PROG Pin Configuration
      3. 8.3.3  Device Power Up from Battery without Input Source
      4. 8.3.4  Device Power Up from Input Source
        1. Power Up REGN LDO
        2. Poor Source Qualification
        3. ILIM_HIZ Pin
        4. Default VINDPM Setting
        5. Input Source Type Detection
          1. D+/Dā€“ Detection Sets Input Current Limit
          2. HVDCP Detection Procedure
          3. Connector Fault Detection
      5. 8.3.5  Dual-Input Power Mux
        1. ACDRV Turn On Condition
        2. VBUS Input Only
        3. One ACFET-RBFET
        4. Two ACFETs-RBFETs
      6. 8.3.6  Buck-Boost Converter Operation
        1. Force Input Current Limit Detection
        2. Input Current Optimizer (ICO)
        3. Maximum Power Point Tracking for Small PV Panel
        4. Pulse Frequency Modulation (PFM)
        5. Device HIZ State
      7. 8.3.7  USB On-The-Go (OTG)
        1. OTG Mode to Power External Devices
        2. Backup Power Supply Mode
        3. Backup Mode with Dual Input Mux
      8. 8.3.8  Power Path Management
        1. Narrow VDC Architecture
        2. Dynamic Power Management
      9. 8.3.9  Battery Charging Management
        1. Autonomous Charging Cycle
        2. Battery Charging Profile
        3. Charging Termination
        4. Charging Safety Timer
        5. Thermistor Qualification
          1. JEITA Guideline Compliance in Charge Mode
          2. Cold/Hot Temperature Window in OTG Mode
      10. 8.3.10 Integrated 16-Bit ADC for Monitoring
      11. 8.3.11 Status Outputs ( STAT, and INT)
        1. Charging Status Indicator (STAT Pin)
        2. Interrupt to Host ( INT)
      12. 8.3.12 Ship FET Control
        1. Shutdown Mode
        2. Ship Mode
        3. System Power Reset
      13. 8.3.13 Protections
        1. Voltage and Current Monitoring
          1.  VAC Over-voltage Protection (VAC_OVP)
          2.  VBUS Over-voltage Protection (VBUS_OVP)
          3.  VBUS Under-voltage Protection (POORSRC)
          4.  System Over-voltage Protection (VSYS_OVP)
          5.  System Short Protection (VSYS_SHORT)
          6.  Battery Over-voltage Protection (VBAT_OVP)
          7.  Battery Over-current Protection (IBAT_OCP)
          8.  Input Over-current Protection (IBUS_OCP)
          9.  OTG Over-voltage Protection (OTG_OVP)
          10. OTG Under-voltage Protection (OTG_UVP)
        2. Thermal Regulation and Thermal Shutdown
      14. 8.3.14 Serial Interface
        1. Data Validity
        2. START and STOP Conditions
        3. Byte Format
        4. Acknowledge (ACK) and Not Acknowledge (NACK)
        5. Slave Address and Data Direction Bit
        6. Single Write and Read
        7. Multi-Write and Multi-Read
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
      2. 8.4.2 Register Bit Reset
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. PV Panel Selection
        2. Inductor Selection
        3. Input (VBUS / PMID) Capacitor
        4. Output (VSYS) Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Ship FET Control

The charger provides an N-FET driving pin (SDRV) to control an external ship FET. The SDRV pin is the output of a charge pump that provides 100 nA typical drive current to drive the ship FET gate to typically 5-V above the battery voltage. When this ship FET is off, it removes leakage current from the battery to the system. The ship FET is controlled by the SDRV_CTRL[1:0] register bits, to support the shutdown mode, ship mode and the system power reset.

  • IDLE Mode when SDRV_CTRL[1:0] = 00, POR default. The external ship FET is fully on, I2C is enabled. The internal BATFET status is determined by the charging status. This mode is valid with adapter present, during forward charging, in OTG mode or in the battery only condition.
  • Shutdown Mode when SDRV_CTRL[1:0] = 01. The ship FET turns off. The I2C is disabled. The charger is totally shutdown and can only be woken up by an adapter plug-in. This mode can only be entered when no adapter is present. If SDRV_CTRL[1:0] is written to 01 with an adapter present, the write is ignored.
  • Ship Mode when SDRV_CTRL[1:0] = 10. The ship FET The ship FET turns off. The I2C is still enabled. The charger can be woken up by setting SDRV_CTRL[1:0] back to 00, or pulling the QON pin low, or an adapter plug-in. This mode can only be entered when no adapter is present. If SDRV_CTRL[1:0] is written to 01 with an adapter present, the write is ignored.
  • System Power Reset when SDRV_CTRL[1:0] = 11. The ship FET is turned off for typical 350ms to reset the system power (converter goes to HIZ mode if VBUS is high), then the ship FET is fully turned on again. The BATFET keeps the status unchanged during the system power reset. After the reset is done, SDRV_CTRL[1:0] goes back to 00.

When the host changes SDRV_CTRL[1:0] from 00 to the other values, the charger turns off the ship FET immediately or delays by tSM_DLY as configured by SDRV_DLY bit. The application diagram when the battery is connected to the charger through an external ship FET is illustrated in the figure below.

GUID-44FE5CF9-EF02-4531-9576-036D7C082CA5-low.gif Figure 8-15 The Application Diagram for the External Ship FET