SNVSCF4 July   2025 LM25139-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Wettable Flanks
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings 
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN )
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC)
      3. 6.3.3  Precision Enable (EN)
      4. 6.3.4  Power-Good Monitor (PG)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Dual Random Spread Spectrum (DRSS)
      7. 6.3.7  Soft Start
      8. 6.3.8  Output Voltage Setpoint (FB)
      9. 6.3.9  Minimum Controllable On Time
      10. 6.3.10 Error Amplifier and PWM Comparator (FB)
      11. 6.3.11 Slope Compensation
      12. 6.3.12 Inductor Current Sense (ISNS, VOUT)
        1. 6.3.12.1 Shunt Current Sensing
        2. 6.3.12.2 Inductor DCR Current Sensing
        3. 6.3.12.3 Hiccup-Mode Current Limiting
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode
      2. 6.4.2 Forced PWM and Synchronization (FPWM/SYNC)
      3. 6.4.3 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 Power MOSFETs
        5. 7.1.1.5 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1 – High Efficiency 2.2MHz Synchronous Buck Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Buck Inductor
          3. 7.2.1.2.3 Current-Sense Components
          4. 7.2.1.2.4 Output Capacitors
          5. 7.2.1.2.5 Input Capacitors
          6. 7.2.1.2.6 Frequency Set Resistor
          7. 7.2.1.2.7 Feedback Resistors
          8. 7.2.1.2.8 Compensation Components
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2 – High-Efficiency, 440kHz, Synchronous Buck Regulator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Stage Layout
        2. 7.4.1.2 Gate Drive Layout
        3. 7.4.1.3 PWM Controller Layout
        4. 7.4.1.4 Thermal Design and Layout
        5. 7.4.1.5 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 Low-EMI Design Resources
        2. 8.2.1.2 Thermal Design Resources
        3. 8.2.1.3 PCB Layout Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

Connect the exposed pad to AGND and PGND on the PCB.
Figure 4-1 16-Pin RGT Package VQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 VIN P Supply voltage input source for the VCC regulator
2 RT I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100kHz and 3.2MHz with DRSS disabled. A resistor from RT to VCC sets the oscillator frequency between 100kHz and 3.2MHz with DRSS enabled.
3 FPWM/SYNC I Connect FPWM/SYNC to GND to enable diode emulation mode. Connect FPWM/SYNC to VCC to operate the LM25139-Q1 in forced PWM (FPWM) mode with conduction at light load. FPWM/SYNC can also be used to synchronize the controller to an external clock. Place the LM25139-Q1 into standby mode by applying an external clock to FPWM/SYNC while EN is low.
4 AGND P Analog ground connection. Ground return for the internal voltage referenced analog circuits.
5 COMP O Transconductance error amplifier. Connect the compensation network for COMP to AGND.
6 FB I Connect FB to VCC to set the output voltage to 3.3V. Connect FB using a 24.9kΩ or 24kΩ to VCC to set the output voltage to 5V. Install a resistor divider from VOUT to AGND to set the output voltage set point between 0.8V and 36V. The regulation voltage at FB is 0.8V.
7 VOUT I Output voltage sense and the current sense amplifiers input. Connect VOUT to the output side of the current sense resistor.
8 ISNS I Current sense amplifier input. Connect this pin to the inductor side of the external current sense resistor.
9 PG O An open collector output that goes low if VOUT is outside the specified regulation window.
10 VCC P VCC bias pin. Connect a ceramic capacitor between VCC and PGND
11 PGND G Power ground connection pin for the low-side power MOSFET gate driver.
12 LO O Low-side power MOSFET gate driver output.
13 SW P Switch node of the buck regulator and high-side gate driver return. Connect to the bootstrap capacitor, the source terminal of the high-side MOSFT, and the drain terminal of the low-side MOSFET.
14 HO O High-side power MOSFET gate driver output.
15 CBOOT P High-side driver supply for bootstrap gate driver.
16 EN I An active-high precision input with rising threshold of 1V and hysteresis current of 11μA. If the EN voltage is less than 0.5V, the LM25139-Q1 is in shutdown mode.
(1) P = Power, G = Ground, I = Input, O = Output