SNVSCF4 July   2025 LM25139-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Wettable Flanks
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings 
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN )
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC)
      3. 6.3.3  Precision Enable (EN)
      4. 6.3.4  Power-Good Monitor (PG)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Dual Random Spread Spectrum (DRSS)
      7. 6.3.7  Soft Start
      8. 6.3.8  Output Voltage Setpoint (FB)
      9. 6.3.9  Minimum Controllable On Time
      10. 6.3.10 Error Amplifier and PWM Comparator (FB)
      11. 6.3.11 Slope Compensation
      12. 6.3.12 Inductor Current Sense (ISNS, VOUT)
        1. 6.3.12.1 Shunt Current Sensing
        2. 6.3.12.2 Inductor DCR Current Sensing
        3. 6.3.12.3 Hiccup-Mode Current Limiting
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode
      2. 6.4.2 Forced PWM and Synchronization (FPWM/SYNC)
      3. 6.4.3 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 Power MOSFETs
        5. 7.1.1.5 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1 – High Efficiency 2.2MHz Synchronous Buck Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Buck Inductor
          3. 7.2.1.2.3 Current-Sense Components
          4. 7.2.1.2.4 Output Capacitors
          5. 7.2.1.2.5 Input Capacitors
          6. 7.2.1.2.6 Frequency Set Resistor
          7. 7.2.1.2.7 Feedback Resistors
          8. 7.2.1.2.8 Compensation Components
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2 – High-Efficiency, 440kHz, Synchronous Buck Regulator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Stage Layout
        2. 7.4.1.2 Gate Drive Layout
        3. 7.4.1.3 PWM Controller Layout
        4. 7.4.1.4 Thermal Design and Layout
        5. 7.4.1.5 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 Low-EMI Design Resources
        2. 8.2.1.2 Thermal Design Resources
        3. 8.2.1.3 PCB Layout Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1.4 Thermal Design and Layout

The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO regulator is greatly affected by the following:

  • Average gate drive current requirements of the power MOSFETs
  • Switching frequency
  • Operating input voltage (affecting bias regulator LDO voltage drop and hence the power dissipation)
  • Thermal characteristics of the package and operating environment

For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The LM25139-Q1 controller is available in a small, 3mm × 3mm 16-pin RGT PowerPAD™ integrated circuit package to cover a range of application requirements. Section 7.4.1.4 summarizes the thermal metrics of this package.

The 16-pin RGT package offers a means of removing heat from the semiconductor die through the exposed thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any leads of the package, the exposed pad of the package is thermally connected to the substrate of the LM25139-Q1 device (ground). This connection allows a significant improvement in heat sinking, and the PCB designed with thermal lands, thermal vias, and a ground plane to complete the heat removal subsystem becomes imperative. The exposed pad of the LM25139-Q1 is soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the thermal resistance to a very low value.

Numerous vias with a 0.3mm diameter connected from the thermal land to the internal and solder-side ground plane or planes are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the PCB layer below the power components. Not only does this action provide a plane for the power stage currents to flow but this action also represents a thermally conductive path away from the heat generating devices.

The thermal characteristics of the MOSFETs also are significant. The drain pads of the high-side MOSFETs are normally connected to a VIN plane for heat sinking. The drain pads of the low-side MOSFETs are tied to the SW plane, but the SW plane area is purposely kept as small as possible to mitigate EMI concerns.