This design example senses the output current across the DCR of the inductor. When
using DCR current sensing, matching the time constant of the sense network with the
time constant of the inductor such that the voltage across the isense capacitor
replicates the voltage across the inductor is important. Use the following steps to
achieve accurate DCR sensing:
- Use Equation 32 to calculate the sense resistor by matching the inductor time constant to the
sensing time constant.
Equation 32.
- Use Equation 33 to calculate the current limit given the DCR of the inductor.
Equation 33.
where
- VCS-TH is the
60mV current limit threshold.
- Place the sense resistor and capacitor close to the inductor.
- Use Kelvin-sense connections, and route the sense lines differentially from the
sense network to the LM25139-Q1.
- The CS-to-output propagation
delay (related to the current limit comparator, internal logic, and power MOSFET
gate drivers) causes the peak current to increase above the calculated current
limit threshold. For a total propagation delay tDELAY-ISNS of 70ns,
use Equation 34 to calculate the worst-case peak inductor current with the output shorted.
Equation 34.
- Based on the result, choose an inductor with a saturation current of 18A or
greater across the full operating temperature range.
The DCR current sense configuration is dependent on the inductor DCR, therefore,
choosing an inductor with DCR characteristics which align with the desired current
limit of the application is important. The saturation current of the inductor also
must be greater than the expected current limit.
When using a series sense resistor,
use the following procedure instead:
- Calculate the current-sense resistance based on a
maximum peak current capability of at least 25% higher than the peak inductor
current at full load to provide sufficient margin during start-up and load-on
transients. Use Equation 35 to calculate the current sense resistances.
Equation 35.
- Select a standard resistance value of 5mΩ for the
shunt. An 0508 footprint component with wide aspect ratio termination design
provides 1W power rating, low parasitic series inductance, and compact PCB
layout. Carefully adhere to the layout guidelines in Section 7.4.1 to make sure that noise and DC errors do not corrupt the differential
current-sense voltages measured at the ISNS+ and VOUT pins.
- Place the shunt resistor close to the inductor.
- Use Kelvin-sense connections, and route the sense
lines differentially from the shunt to the LM25139-Q1.
- The CS-to-output propagation delay (related to
the current limit comparator, internal logic, and power MOSFET gate drivers)
causes the peak current to increase above the calculated current limit
threshold. For a total propagation delay tDELAY-ISNS of 70ns, use
Equation 36 to calculate the worst-case peak inductor current with the
output shorted.
Equation 36.
- Based on this result, select an inductor with
saturation current greater than 16A across the full operating temperature
range.