SNVSCF4 July   2025 LM25139-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
    1. 4.1 Wettable Flanks
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings 
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN )
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC)
      3. 6.3.3  Precision Enable (EN)
      4. 6.3.4  Power-Good Monitor (PG)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Dual Random Spread Spectrum (DRSS)
      7. 6.3.7  Soft Start
      8. 6.3.8  Output Voltage Setpoint (FB)
      9. 6.3.9  Minimum Controllable On Time
      10. 6.3.10 Error Amplifier and PWM Comparator (FB)
      11. 6.3.11 Slope Compensation
      12. 6.3.12 Inductor Current Sense (ISNS, VOUT)
        1. 6.3.12.1 Shunt Current Sensing
        2. 6.3.12.2 Inductor DCR Current Sensing
        3. 6.3.12.3 Hiccup-Mode Current Limiting
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode
      2. 6.4.2 Forced PWM and Synchronization (FPWM/SYNC)
      3. 6.4.3 Thermal Shutdown
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 Power MOSFETs
        5. 7.1.1.5 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1 – High Efficiency 2.2MHz Synchronous Buck Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Buck Inductor
          3. 7.2.1.2.3 Current-Sense Components
          4. 7.2.1.2.4 Output Capacitors
          5. 7.2.1.2.5 Input Capacitors
          6. 7.2.1.2.6 Frequency Set Resistor
          7. 7.2.1.2.7 Feedback Resistors
          8. 7.2.1.2.8 Compensation Components
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2 – High-Efficiency, 440kHz, Synchronous Buck Regulator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Stage Layout
        2. 7.4.1.2 Gate Drive Layout
        3. 7.4.1.3 PWM Controller Layout
        4. 7.4.1.4 Thermal Design and Layout
        5. 7.4.1.5 Ground Plane Design
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 Low-EMI Design Resources
        2. 8.2.1.2 Thermal Design Resources
        3. 8.2.1.3 PCB Layout Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Current-Sense Components

This design example senses the output current across the DCR of the inductor. When using DCR current sensing, matching the time constant of the sense network with the time constant of the inductor such that the voltage across the isense capacitor replicates the voltage across the inductor is important. Use the following steps to achieve accurate DCR sensing:

  1. Use Equation 32 to calculate the sense resistor by matching the inductor time constant to the sensing time constant.
    Equation 32. R c s = L O C C S × R D c R = 0.68 μ H 0.1 μ F × 4 m = 1.7 k
  2. Use Equation 33 to calculate the current limit given the DCR of the inductor.
    Equation 33. I C L = V C S - T H R D C R = 60 m V 4 m = 15 A

    where

    • VCS-TH is the 60mV current limit threshold.
  3. Place the sense resistor and capacitor close to the inductor.
  4. Use Kelvin-sense connections, and route the sense lines differentially from the sense network to the LM25139-Q1.
  5. The CS-to-output propagation delay (related to the current limit comparator, internal logic, and power MOSFET gate drivers) causes the peak current to increase above the calculated current limit threshold. For a total propagation delay tDELAY-ISNS of 70ns, use Equation 34 to calculate the worst-case peak inductor current with the output shorted.
    Equation 34. I L O - P K ( S C ) = V C S - T H R D C R + V I N ( m a x ) × t D E L A Y - I S N S L O = 60 m V 4 m + 18 V × 70 n s 0.68 μ H = 16.8 A
  6. Based on the result, choose an inductor with a saturation current of 18A or greater across the full operating temperature range.

The DCR current sense configuration is dependent on the inductor DCR, therefore, choosing an inductor with DCR characteristics which align with the desired current limit of the application is important. The saturation current of the inductor also must be greater than the expected current limit.

When using a series sense resistor, use the following procedure instead:

  1. Calculate the current-sense resistance based on a maximum peak current capability of at least 25% higher than the peak inductor current at full load to provide sufficient margin during start-up and load-on transients. Use Equation 35 to calculate the current sense resistances.
    Equation 35. R s = V C S - T H 1.25 × I L O ( P K ) = 60 m V 1.25 × 9.2 A = 5.2 m
  2. Select a standard resistance value of 5mΩ for the shunt. An 0508 footprint component with wide aspect ratio termination design provides 1W power rating, low parasitic series inductance, and compact PCB layout. Carefully adhere to the layout guidelines in Section 7.4.1 to make sure that noise and DC errors do not corrupt the differential current-sense voltages measured at the ISNS+ and VOUT pins.
  3. Place the shunt resistor close to the inductor.
  4. Use Kelvin-sense connections, and route the sense lines differentially from the shunt to the LM25139-Q1.
  5. The CS-to-output propagation delay (related to the current limit comparator, internal logic, and power MOSFET gate drivers) causes the peak current to increase above the calculated current limit threshold. For a total propagation delay tDELAY-ISNS of 70ns, use Equation 36 to calculate the worst-case peak inductor current with the output shorted.
    Equation 36. I L O - P K ( S C ) = V C S - T H R S + V I N ( m a x ) × t D E L A Y - I S N S L O = 60 m V 5 m + 18 V × 70 n s 0.68 μ H = 13.8 A
  6. Based on this result, select an inductor with saturation current greater than 16A across the full operating temperature range.