SNVSCF4 July   2025 LM25139-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Wettable Flanks
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings 
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN )
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC)
      3. 6.3.3  Precision Enable (EN)
      4. 6.3.4  Power-Good Monitor (PG)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Dual Random Spread Spectrum (DRSS)
      7. 6.3.7  Soft Start
      8. 6.3.8  Output Voltage Setpoint (FB)
      9. 6.3.9  Minimum Controllable On Time
      10. 6.3.10 Error Amplifier and PWM Comparator (FB)
      11. 6.3.11 Slope Compensation
      12. 6.3.12 Inductor Current Sense (ISNS, VOUT)
        1. 6.3.12.1 Shunt Current Sensing
        2. 6.3.12.2 Inductor DCR Current Sensing
        3. 6.3.12.3 Hiccup-Mode Current Limiting
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode
      2. 6.4.2 Forced PWM and Synchronization (FPWM/SYNC)
      3. 6.4.3 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 Power MOSFETs
        5. 7.1.1.5 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1 – High Efficiency 2.2MHz Synchronous Buck Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Buck Inductor
          3. 7.2.1.2.3 Current-Sense Components
          4. 7.2.1.2.4 Output Capacitors
          5. 7.2.1.2.5 Input Capacitors
          6. 7.2.1.2.6 Frequency Set Resistor
          7. 7.2.1.2.7 Feedback Resistors
          8. 7.2.1.2.8 Compensation Components
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2 – High-Efficiency, 440kHz, Synchronous Buck Regulator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Stage Layout
        2. 7.4.1.2 Gate Drive Layout
        3. 7.4.1.3 PWM Controller Layout
        4. 7.4.1.4 Thermal Design and Layout
        5. 7.4.1.5 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 Low-EMI Design Resources
        2. 8.2.1.2 Thermal Design Resources
        3. 8.2.1.3 PCB Layout Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4.2 Forced PWM and Synchronization (FPWM/SYNC)

A synchronous buck regulator implemented with a low-side synchronous MOSFET rather than a diode has the capability to sink negative current from the output during conditions of, light-load, output overvoltage, and prebias start-up conditions. The LM25139-Q1 provides a diode emulation feature, also called PFM mode, that can be enabled to prevent reverse (drain-to-source) current flow in the low-side MOSFET. When configured for PFM mode, the low-side MOSFET is switched off when reverse current flow is detected by sensing the inductor current (VISNS – VOUT) using either current sense resistor or inductor DCR sensing method. The sensed inductor current is compared against a zero-cross threshold (5.5mV) to indicate reverse current flow. In PFM mode, the peak inductor current is forced to be at a minimum of 20% of the current limit. The benefit of this configuration is lower power loss during light-load conditions; the disadvantage of PFM mode is slower light-load transient response.

Configure PFM using the FPWM/SYNC pin. To enable PFM and thus achieve low-IQ current at light loads, connect FPWM/SYNC to GND. If FPWM with continuous conduction mode (CCM) operation is desired, tie FPWM/SYNC to VCC. Note that PFM mode is automatically engaged to prevent reverse current flow during a prebias start-up. If the device has been configured to operate in FPWM mode, the device still starts up in PFM mode and takes 1000 cycles of switching pulses to transition from PFM to FPWM mode during start-up.

The LM25139-Q1 has a 35μs typical deglitch filter to transition from FPWM to PFM mode. After the deglitch filter expires, the peak inductor current is forced to be at a minimum of 20% of the current limit and a zero current threshold of 5.5mV is enabled. The transition from PFM mode to FPWM mode is in two stages. In first stage the minimum peak current limit of 20% is removed immediately. Subsequently, the 5.5mV zero current threshold is linearly reduced to a negative current limit of 30mV over 1000 high-side FET switching cycles.

To synchronize the LM25139-Q1 to an external source, apply a logic-level clock to FPWM/SYNC. The LM25139-Q1 can be synchronized to ±20% of the RT programmed frequency up to a maximum of 3.2MHz. If there is an RT resistor and a synchronization signal, the LM25139-Q1 ignores the RT resistor and synchronizes to the external clock. Under low-VIN conditions when the minimum off time is reached, the synchronization signal is ignored, allowing the switching frequency to be reduced to maintain output voltage regulation.

The LM25139-Q1 can be placed into standby mode by applying an external clock on the FPWM/SYNC while the EN voltage is low. This action turns on the VCC regulator to allow for a faster turn-on time when EN is driven above 1V.