SNVSCF4 July   2025 LM25139-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Wettable Flanks
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings 
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Voltage Range (VIN )
      2. 6.3.2  High-Voltage Bias Supply Regulator (VCC)
      3. 6.3.3  Precision Enable (EN)
      4. 6.3.4  Power-Good Monitor (PG)
      5. 6.3.5  Switching Frequency (RT)
      6. 6.3.6  Dual Random Spread Spectrum (DRSS)
      7. 6.3.7  Soft Start
      8. 6.3.8  Output Voltage Setpoint (FB)
      9. 6.3.9  Minimum Controllable On Time
      10. 6.3.10 Error Amplifier and PWM Comparator (FB)
      11. 6.3.11 Slope Compensation
      12. 6.3.12 Inductor Current Sense (ISNS, VOUT)
        1. 6.3.12.1 Shunt Current Sensing
        2. 6.3.12.2 Inductor DCR Current Sensing
        3. 6.3.12.3 Hiccup-Mode Current Limiting
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode
      2. 6.4.2 Forced PWM and Synchronization (FPWM/SYNC)
      3. 6.4.3 Thermal Shutdown
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Power Train Components
        1. 7.1.1.1 Buck Inductor
        2. 7.1.1.2 Output Capacitors
        3. 7.1.1.3 Input Capacitors
        4. 7.1.1.4 Power MOSFETs
        5. 7.1.1.5 EMI Filter
      2. 7.1.2 Error Amplifier and Compensation
    2. 7.2 Typical Applications
      1. 7.2.1 Design 1 – High Efficiency 2.2MHz Synchronous Buck Regulator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
          1. 7.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 7.2.1.2.2 Buck Inductor
          3. 7.2.1.2.3 Current-Sense Components
          4. 7.2.1.2.4 Output Capacitors
          5. 7.2.1.2.5 Input Capacitors
          6. 7.2.1.2.6 Frequency Set Resistor
          7. 7.2.1.2.7 Feedback Resistors
          8. 7.2.1.2.8 Compensation Components
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Design 2 – High-Efficiency, 440kHz, Synchronous Buck Regulator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Stage Layout
        2. 7.4.1.2 Gate Drive Layout
        3. 7.4.1.3 PWM Controller Layout
        4. 7.4.1.4 Thermal Design and Layout
        5. 7.4.1.5 Ground Plane Design
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
        1. 8.2.1.1 Low-EMI Design Resources
        2. 8.2.1.2 Thermal Design Resources
        3. 8.2.1.3 PCB Layout Resources
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to 150°C. Typical values are at TJ = 25°C and VIN = 12V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY (VIN)
IQ-VIN1 VIN shutdown current VEN = 0V 2.3 4 µA
IQ-VIN2 VIN standby current Non-switching, 0.5V ≤ VEN ≤ 1V 30 48 µA
ISLEEP1 Sleep current, 3.3V VEN = 5V, VVOUT = 3.3V, in regulation, no load, not switching, VFPWM/SYNC = 0V  10 18 µA
ISLEEP2 Sleep current, 5V VEN = 5V, VVOUT = 5V, in regulation, no-load, not switching, VFPWM/SYNC = 0V 11 20 µA
PRECISION ENABLE (EN)
VSDN Shutdown to standby threshold VEN rising 0.5 V
VEN-HIGH Enable voltage rising threshold VEN rising, enable switching 0.95 1.0 1.05 V
IEN-HYS Enable hysteresis VEN = 1.1V –14 –11 –8 µA
INTERNAL LDO (VCC)
VVCC-REG VCC regulation voltage IVCC = 0mA to 90mA 4.7 5 5.3 V
VVCC-UVLO VCC UVLO rising threshold 3.68 3.8 3.9 V
VVCC-HYST VCC UVLO hysteresis 300 mV
IVCC-REG Internal LDO short-circuit current limit 210 mA
REFERENCE VOLTAGE (FB)
VREF Regulated FB voltage 792 800 808 mV
OUTPUT VOLTAGE (VOUT)
VOUT-3.3V–INT 3.3V output voltage setpoint RFB = 0Ω, VIN = 4V to 42V 3.26 3.3 3.33 V
VOUT-5V–INT 5V output voltage setpoint RFB = 24.9kΩ, VIN = 5.5V to 42V 4.93 5.0 5.05 V
ERROR AMPLIFIER (COMP)
gm EA transconductance 1.1 mS
IFB Error amplifier input bias current 100 nA
VCOMP-CLAMP=MAX COMP clamp maximum voltage 2.1 V
ICOMP-SRC EA source current VCOMP = 1V, VFB = 0.68V 115 µA
ICOMP-SINK EA sink current VCOMP = 1V, VFB = 0.92V 115 µA
DUAL RANDOM SPREAD SPECTURM (DRSS)
fm Modulation frequency 7.2 16.6 kHz
ΔfC1 Low-frequency spread spectrum
modulation range 1		 LM25139D5QRGTRQ1 ±5 %
ΔfC2 Low-frequency spread spectrum
modulation range 2		 LM25139QRGTRQ1 ±10 %
FORCED PWM (FPWM/SYNC)
VFPWM-HI  FPWM high detection threshold  1.2 V
VFPWM-LO  FPWM low detection threshold  0.8 V
VZC-PFM Zero-cross threshold (LO off) in PFM –5.5 mV
VZC-FPWM Zero-cross threshold (LO off) in FPWM 30 mV
tPFM-FILTER SYNCIN to PFM mode 13 72 µs
SWITCHING FREQUENCY (RT)
VRT RT pin regulation voltage 10kΩ < RRT < 100kΩ 1 V
FSW2-VCC Switching frequency 2, RT to VCC RT = 10.1kΩ to VCC 2.2 MHz
FSW1 Switching frequency 1  RRT = 53kΩ to AGND  396 440 484 kHz
FSW2 Switching frequency 2 RRT =  10.1kΩ to AGND  2.2 MHz
FSW3 Switching frequency 3 RRT = 237kΩ to  AGND 100 kHz
SLOPE1 Internal slope compensation 1 RRT = 10.1kΩ 1000 mV/µs
tON(min) Minimum on-time VHO – VSW = VCBOOT – VSW 25 ns
tOFF(min) Minimum off-time VHO – VSW = 0V 80 ns
POWER GOOD (PG)
VPG-OV PG OV threshold level  Rising with respect to the regulation voltage 107 110 113.5 %
VPG-UV PG UV threshold level Falling with respect to the regulated voltage 89 92  95 %
VPG-UV-HYST PG UV hysteresis  Rising with respect to the regulated output 3.6 %
VPG-OV-HYST PG OV hysteresis Rising with respect to the regulation voltage 3.6 %
tOV-DLY PG OV filter time VOUT rising 25 µs
tUV-DLY PG UV filter time VOUT falling 25 µs
VPG-OL PG voltage Open collector, IPG = 4mA 0.04 0.14 0.8 V
STARTUP (Soft Start)
tSS-INT Internal fixed soft-start time 1.5 3 4.2 ms
BOOT CIRCUIT (CBOOT)
VBOOT-DROP Internal diode forward drop ICBOOT = 20mA, VCC to CBOOT 0.8 V
IBOOT CBOOT to SW quiescent current, not switching VEN = 5V, VCBOOT – VSW = 5V 9 µA
VBOOT-SW-UV-R CBOOT to SW UVLO rising threshold VCBOOT – VSW rising 2.9 V
VBOOT-SW-UV-F CBOOT to SW UVLO falling threshold VCBOOT – VSW falling 2.6 V
VBOOT-SW-UV-HYS CBOOT to SW UVLO hysteresis 330 mV
HIGH-SIDE GATE DRIVER (HO)
VHO-HIGH HO high-state output voltage IHO = –100mA, VHO-HIGH = VCBOOT – VHO 120 mV
VHO-LOW HO low-state output voltage IHO = 100mA 60 mV
IHO-SRC HO peak source current VHO = VSW = 0V, VCBOOT = VVCC = 5V 1.65 A
IHO-SINK HO peak sink current VVCC = 5V 2.4 A
LOW-SIDE GATE DRIVER (LO)
VLO-HIGH LO high-state output voltage ILO = –100mA 124 mV
VLO-LOW LO low-state output voltage ILO = 100mA 60 mV
ILO-SRC LO peak source current VLO = VSW = 0V, VVCC = 5V 1.65 A
ILO-SINK LO peak sink current VVCC = 5V 2.4 A
ADAPTIVE DEADTIME CONTROL
tDEAD1 HO off to LO on deadtime 18 ns
tDEAD2 LO off to HO on deadtime 22 ns
INTERNAL HICCUP MODE
HICDLY Hiccup mode activation delay VISNS – VVOUT > 60mV 512 cycles
HICCYCLES HICCUP mode fault VISNS – VVOUT > 60mV 16384 cycles
OVERCURRENT PROTECTION
VCS-TH Current limit threshold Measured from ISNS to VOUT 52 60 68 mV
tDELAY-ISNS ISNS delay to output 70 ns
GCS CS amplifier gain  10 V/V
IBIAS-ISNS CS amplifier input bias current  1.2 µA
THERMAL SHUTDOWN
TJ-SHD Thermal shutdown threshold (1) Temperature rising 175 °C
TJ-HYS Thermal shutdown hysteresis (1) 15 °C
(1) Specified by design. Not production tested.