SNAS800 July 2021 LMX1204
The high frequency capability and extremely low jitter of this device, makes a great solution to clock precision, high-frequency data converters without degradation to the signal-to-noise ratio. Each of the 4 high frequency clock outputs and additional LOGICLK output with larger divider range, is paired with a SYSREF output clock signal. The SYSREF signal for JESD interfaces can either be internally generated or passed in as an input and re-clocked to the device clocks. For data converter clocking applications, it is critical to have the jitter of the clock be less than the aperture jitter of the data converter. In applications where more than 4 data converters need to be clocked, a variety of cascading architectures can be developed using multiple devices to distribute all the high frequency clocks and SYSREF signals required. With 30 fs of additive jitter and a noise floor of -160 dBc/Hz, this device combined with an ultra-low noise reference clock source is an exemplary solution for clocking data converters, especially when sampling above 3 GHz.
|PART NUMBER||PACKAGE||BODY SIZE|
|LMX1204||VQFN (40)||6.00 mm × 6.00 mm|
|PART NUMBER||MULTIPLIER OUTPUT|
|LMX1204||3.2 to 6.4 GHz|