SNAS800
July 2021
LMX1204
ADVANCE INFORMATION
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.1.1
Range of Dividers and Multiplier
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Power On Reset
7.3.2
Clock Outputs
7.3.2.1
Clock Output Buffers
7.3.2.2
Clock MUX
7.3.2.3
Clock Divider
7.3.2.4
Clock Multiplier
7.3.3
SYSREF
7.3.3.1
SYSREF Output Buffers
7.3.3.1.1
SYSREF Output Buffer for Main Clocks
7.3.3.1.2
SYSREF Output Buffer for LOGICLK
7.3.3.2
SYSREF Frequency and Delay Generation
7.3.3.3
SYSREFREQ pins
7.3.3.3.1
SYSREFREQ Pins Common Mode Voltage
7.3.3.3.2
SYSREFREQ Pin Windowing Feature
7.3.3.4
SYNC Feature
7.3.4
LOGICLK Output
7.3.4.1
LOGICLK Output Format
7.3.4.2
LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
7.4
Device Functional Modes
8
Application and Implementation
8.1
Applications Information
8.1.1
Current Consumption
8.1.2
Treatment of Unused Pins
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
9
Power Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
Support Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
12.1
Package Option Addendum
12.2
Tape and Reel Information
Package Options
Mechanical Data (Package|Pins)
RHA|40
MPQF135D
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snas800_oa
11.5
Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.