SNAS800 July   2021 LMX1204

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Range of Dividers and Multiplier
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power On Reset
      2. 7.3.2 Clock Outputs
        1. 7.3.2.1 Clock Output Buffers
        2. 7.3.2.2 Clock MUX
        3. 7.3.2.3 Clock Divider
        4. 7.3.2.4 Clock Multiplier
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Output Buffers
          1. 7.3.3.1.1 SYSREF Output Buffer for Main Clocks
          2. 7.3.3.1.2 SYSREF Output Buffer for LOGICLK
        2. 7.3.3.2 SYSREF Frequency and Delay Generation
        3. 7.3.3.3 SYSREFREQ pins
          1. 7.3.3.3.1 SYSREFREQ Pins Common Mode Voltage
          2. 7.3.3.3.2 SYSREFREQ Pin Windowing Feature
        4. 7.3.3.4 SYNC Feature
      4. 7.3.4 LOGICLK Output
        1. 7.3.4.1 LOGICLK Output Format
        2. 7.3.4.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Applications Information
      1. 8.1.1 Current Consumption
      2. 8.1.2 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

SYSREF Frequency and Delay Generation

The SYSREF circuitry can produce an output signal that is synchronized to fCLKIN. This output can be a single pulse, series of pulses, or a continuous stream of pulses. In generator mode, the SYSREF_DIV_PRE and SYSREF_DIV values are used to divide the CLKIN frequency to a lower frequency that is reclocked to the output. In repeater mode, this signal is instead input at the SYSREFREQ pins. For each of the outputs, there is an independent delay control.

Table 7-6 SYSREF Modes
SYSREF_MODE Description
0 Generator Mode (Continuous)

Internal generator creates a continuous stream of SYSREF pulses. The SYSREFREQ pins can be used to turn portions of the SYSREF circuitry without disrupting the synchronization of the SYSREF dividers. These pins need to be logic high for a SYSREF output to come out.

1 Generator Mode (Pulser)

Internal generator generates a burst of 1 - 16 pulses that is set by SYSREF_PULSE_COUNT that occurs after a rising edge on the SYSREFREQ pins

2 Repeater Mode

SYSREFREQ pins are reclocked at the clock outputs.

GUID-20210304-CA0I-CPNP-XDKH-N9BF57M2ZJ4S-low.gif Figure 7-4 SYSREF Generator Diagram

For the frequency of the SYSREF output for continuous SYSREF output in generator mode, the SYSREF_DIV_PRE divider is necessary to ensure that the input of the SYSREF_DIV divider is not more than 3.2 GHz.

Table 7-7 SYSREF_DIV_PRE Setup
fCLKIN SYSREF_DIV_PRE TOTAL SYSREF DIVIDE RANGE
3.2 GHz or Less 1, 2, or 4 2,3,4,...16380
3.2 GHz < fCLKIN <= 6.4 GHz 2 or 4 4,6,8, … 16380
fCLKIN > 6.4 GHz 4 8,12,16, … 16380

For the delay, the input clock frequency is divided by SYSREF_DLY_DIV to generate fINTERPOLATOR, which has a restricted range as shown in Table 7-8. Note also that when SYSREF_MODE is set to continuous or pulser mode, the SYSREF output frequency must be a multiple of the phase interpolator frequency.

fINTERPOLATOR % fSYSREF = 0.

Table 7-8 SYSREF Delay Setup
fCLKIN SYSREF_DLY_DIV SYSREFx_DLY_ADJ fINTERPOLATOR
6.4 to 12.8 GHz 16 0 0.4 to 0.8 GHz
3.2 to 6.4 GHz 8 0 0.4 to 0.8 GHz
1.6 to 3.2 GHz 4 0 0.4 to 0.8 GHz
0.8 to 1.6 GHz 2 0 0.4 to 0.8 GHz
0.4 to 0.8 GHz 2 1 0.2 to 0.4 GHz
0.3 to 0.4 GHz 2 2 0.15 to 0.2 GHz

The maximum delay is equal to the phase interpolator period and there are 4x127 = 508 different delay steps. Use Equation 1 to calculate the size of each step.

Equation 1. DelayStepSize = 1/( fINTERPOLATOR × 508) = SYSREF_DLY_DIV/( fCLKIN × 508)

The total delay is calculated as with Equation 2.

Equation 2. TotalDelay=DelayStepSize × StepNumber

The number of steps can be calculated as shown in Table 7-9.

Table 7-9 Calculation of StepNumber
SYSREFx_DLY_QUAD StepNumber
3 127 - SYSREFx_DLY_I
2 254 - SYSREFx_DLY_Q
0 381 - SYSREFx_DLY_I
1 508 - SYSREFx_DLY_Q

The SYSREF_DLY_BYP field selects between the delay generator output and the repeater mode bypass signal. When using SYSREF_MODE set to continuous or pulser, it is recommended to set this to generator mode and when SYSREF_MODE is set to repeater mode, it is recommended to set this to bypass mode.