SNAS800B July   2021  – February 2024 LMX1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier and Filter Modes
          1. 6.3.3.4.1 General Information About the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Using the x1 Clock Multiplier as a Filter
          5. 6.3.3.4.5 Lock Detect for the Clock Multiplier
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_SPI Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
      7. 6.3.7 SYNC Feature
    4. 6.4 Device Functional Modes
  8. 7 Register Map
    1. 7.1 LMX1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SYSREFREQ Input Configuration
      2. 8.1.2 Reducing SYSREF Common Mode Voltages
      3. 8.1.3 Current Consumption
      4. 8.1.4 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.6.2 SYSREF Frequency and Delay Generation

The SYSREF circuitry can produce an output signal that is synchronized to fCLKIN. This output can be a single pulse, series of pulses, or a continuous stream of pulses. In generator mode, the SYSREF_DIV_PRE and SYSREF_DIV values are used to divide the CLKIN frequency to a lower frequency that is reclocked to the output. In repeater mode, this signal is instead input at the SYSREFREQ pins. For each of the outputs, there is an independent delay control.

Table 6-11 SYSREF Modes
SYSREF_MODE DESCRIPTION
0 Generator Mode (Continuous)

Internal generator creates a continuous stream of SYSREF pulses. The SYSREFREQ pins or the SYSREFREQ_SPI field can be used to gate the SYSREF divider from the channels for improved noise isolation without disrupting the synchronization of the SYSREF dividers. The SYSREFREQ pins or the SYSREFREQ_SPI field must be high for a SYSREF output to come out.
1 Generator Mode (Pulser)

Internal generator generates a burst of 1 - 16 pulses that is set by SYSREF_PULSE_COUNT that occurs after a rising edge on the SYSREFREQ pins
2 Repeater Mode

SYSREFREQ pins are reclocked to clock outputs and then delayed in accordance to the SYSREF_DELAY_BYPASS field before being sent to the SYSREFOUT outputs.
GUID-20210304-CA0I-CPNP-XDKH-N9BF57M2ZJ4S-low.svg Figure 6-8 SYSREF Generator Diagram

For the frequency of the SYSREF output in generator mode, the SYSREF_DIV_PRE divider is necessary to verify that the input of the SYSREF_DIV divider is not more than 3.2 GHz.

Table 6-12 SYSREF_DIV_PRE Setup
fCLKIN SYSREF_DIV_PRE TOTAL SYSREF DIVIDE RANGE
3.2 GHz or Less ÷1, 2, or 4 ÷2,3,4,...16380
3.2 GHz < fCLKIN ≤ 6.4 GHz ÷2 or 4 ÷4,6,8, … 16380
fCLKIN > 6.4 GHz ÷4 ÷8,12,16, … 16380

For the delay, the input clock frequency is divided by SYSREF_DELAY_DIV to generate fINTERPOLATOR. This has a restricted range as shown in Table 6-13. Note also that when SYSREF_DELAY_BYPASS=0 or 2 (delaygen engaged for generator mode), and SYSREF_MODE = 0 or 1 (a generator mode) the SYSREF output frequency must be a multiple of the phase interpolator frequency.

fINTERPOLATOR % fSYSREF = 0.

Table 6-13 SYSREF Delay Setup
fCLKIN SYSREF_DELAY_DIV SYSREFx_DELAY_SCALE fINTERPOLATOR
6.4 GHz < fCLKIN ≤ 12.8GHz 16 0 0.4 to 0.8 GHz
3.2 GHz < fCLKIN ≤ 6.4 GHz 8 0 0.4 to 0.8 GHz
1.6 GHz < fCLKIN ≤ 3.2 GHz 4 0 0.4 to 0.8 GHz
0.8 GHz < fCLKIN ≤1.6 GHz 2 0 0.4 to 0.8 GHz
0.4 GHz < fCLKIN ≤ 0.8 GHz 2 1 0.2 to 0.4 GHz
0.3 GHz < fCLKIN ≤ 0.4 GHz 2 2 0.15 to 0.2 GHz

The maximum delay is equal to the phase interpolator period and there are 4x127 = 508 different delay steps. Use Equation 2 to calculate the size of each step.

Equation 2. DelayStepSize = 1/( fINTERPOLATOR × 508) = SYSREF_DELAY_DIV/( fCLKIN × 508)

Use Equation 3 to calculate the total delay.

Equation 3. TotalDelay=DelayStepSize × StepNumber

Table 6-14 shows the number of steps for each delay.

Table 6-14 Calculation of StepNumber
SYSREFx_DELAY_PHASE STEPNUMBER
3 127 - SYSREFx_DELAY_I
2 254 - SYSREFx_DELAY_Q
0 381 - SYSREFx_DELAY_I
1 508 - SYSREFx_DELAY_Q

The SYSREF_DELAY_BYPASS field selects between the delay generator output and the repeater mode bypass signal. When SYSREF_MODE is set to continuous or pulser mode, TI recommends to set SYSREF_DELAY_BYPASS to generator mode. If SYSREF_MODE is set to repeater mode, TI recommends to set SYSREF_DELAY_BYPASS to bypass mode.