SNAS800 July   2021 LMX1204

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Range of Dividers and Multiplier
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power On Reset
      2. 7.3.2 Clock Outputs
        1. 7.3.2.1 Clock Output Buffers
        2. 7.3.2.2 Clock MUX
        3. 7.3.2.3 Clock Divider
        4. 7.3.2.4 Clock Multiplier
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Output Buffers
          1. 7.3.3.1.1 SYSREF Output Buffer for Main Clocks
          2. 7.3.3.1.2 SYSREF Output Buffer for LOGICLK
        2. 7.3.3.2 SYSREF Frequency and Delay Generation
        3. 7.3.3.3 SYSREFREQ pins
          1. 7.3.3.3.1 SYSREFREQ Pins Common Mode Voltage
          2. 7.3.3.3.2 SYSREFREQ Pin Windowing Feature
        4. 7.3.3.4 SYNC Feature
      4. 7.3.4 LOGICLK Output
        1. 7.3.4.1 LOGICLK Output Format
        2. 7.3.4.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Applications Information
      1. 8.1.1 Current Consumption
      2. 8.1.2 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
SYSREFREQ Pin Windowing Feature

The SYSREF windowing can be used to internally calibrate the timing between the SYSREFREQ and CLKIN pins in order to optimize setup and hold timing and trim out the device's internal delay mismatch on the SYSREFREQ and CLKIN paths. This feature requires that the timing from the SYSREFREQ rising edge to the CLKIN rising edge is consistent. The timing from the SYSREFREQ rising edge to the CLKIN rising edges can be tracked with the rb_SYSWND field, which is the concatenation of the rb_SYSWND_L and rb_SYSWND_R fields. Once the timing to the rising edge of the CLKIN pin is found, then the SYSREFREQ rising edge can be internally delayed with the SYSWND_OFFSET field.

GUID-20210511-CA0I-X3JH-X8QF-ZN3ZVJSW2J5T-low.gif Figure 7-5 SYSREFREQ Internal Timing Adjustment

General Procedure

  • While programming the windowing feature for the first time, SYSREFREQ needs to be low.
  • Set SYSREF_MODE=2
  • Set SYSWND_DLY according to Table 7-11.
  • Program SYNC_SYSWND_CLR=1 and then SYNC_SYSWND_CLR=0
  • Send a rising edge to the SYSREFREQ pin(s)
  • Read back position with rb_SYSWND_L/R fields to determine timing from the SYSREQREQ rising edge to the next CLKIN rising edge. The number of 0's between the LSB '1' bit and the first series of '11' can be multiplied by the delay determined by SYSWND_DLY to determine the approximate timing to the first rising clock edge.
  • Program SYSWND_OFFSET field in delay steps to maximize margin between left and right rising edges of CLKIN
Table 7-11 SYSWND_DLY
INPUT FREQUENCY RECOMMENDED SYSWND_DLY<1:0> DELAY(ps)
1.4 - 2.7GHz 0 28
2.4 - 4.7 GHz 1 15
3.1 - 5.7 GHz 2 11
4.5 - 12.8 GHz 3 8

For glitch-free output

  • When switching from request mode to windowing mode and back to request mode, keep the SYSREFREQ pin state stays the same. For example, if the SYSREFREQ pin is high (or low) when windowing mode starts, make sure the pin state is high (or low) again after windowing mode ends before programing SRREQ_MODE.
  • The SYSREFREQ pin must be set low when switching from or to SYNC mode.
  • SYSREFREQ → SYSWND → SYNC, mode switching should be performed with SYSREFREQ pin set to low. If the device goes from SYSREF_MODE=1 to 2 with the SYSREFREQ pin high, then the user must come back to SYSREF_MODE=1 and set SYSREFREQ pin low and then switch to SYNC mode. Direct transition with the SYSREFREQ pins high may lead to a glitch at the output.

Other pointers with SYSREF windowing

  • The SYSREFREQ pins need to be held for a minimum of T1 > 3/fCLKIN + 1.6 ns and only after this time rb_SYSWND_L/R fields are valid.
  • If the user infers multiple valid SYSWND_OFFSET values from rb_SYSWND registers to avoid setup-hold violations, choosing the lowest valid SYSWND_OFFSET is recommended to minimize variation over temperature.

If using SYNC feature

  • Only one SYSREFREQ pin rising edge is permitted per 75 input clock cycles
  • SYSREFREQ has to stay high for >6 clock cycles