SNAS800B July   2021  – February 2024 LMX1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier and Filter Modes
          1. 6.3.3.4.1 General Information About the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Using the x1 Clock Multiplier as a Filter
          5. 6.3.3.4.5 Lock Detect for the Clock Multiplier
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_SPI Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
      7. 6.3.7 SYNC Feature
    4. 6.4 Device Functional Modes
  8. 7 Register Map
    1. 7.1 LMX1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SYSREFREQ Input Configuration
      2. 8.1.2 Reducing SYSREF Common Mode Voltages
      3. 8.1.3 Current Consumption
      4. 8.1.4 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Register Map

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
R0 0 0 0 0 0 0 0 0 0 0 0 0 0 POWERDOWN 0 RESET
R2 0 0 0 0 0 0 SMCLK_DIV_PRE SMCLK_EN 0 0 0 1 1
R3 CH3_EN CH2_EN CH1_EN CH0_EN LOGIC_MUTE_CAL CH3_MUTE_CAL CH2_MUTE_CAL CH1_MUTE_CAL CH0_MUTE_CAL 0 0 0 0 SMCLK_DIV
R4 0 0 CLKOUT1_PWR CLKOUT0_PWR SYSREFOUT3_EN SYSREFOUT2_EN SYSREFOUT1_EN SYSREFOUT0_EN CLKOUT3_EN CLKOUT2_EN CLKOUT1_EN CLKOUT0_EN
R5 0 SYSREFOUT2_PWR SYSREFOUT1_PWR SYSREFOUT0_PWR CLKOUT3_PWR CLKOUT2_PWR
R6 LOGICLKOUT_EN SYSREFOUT3_VCM SYSREFOUT2_VCM SYSREFOUT1_VCM SYSREFOUT0_VCM SYSREFOUT3_PWR
R7 0 LOGISYSREFOUT_VCM LOGICLKOUT_VCM LOGISYSREFOUT_PREDRV_PWR LOGICLKOUT_PREDRV_PWR LOGISYSREFOUT_PWR LOGICLKOUT_PWR LOGISYSREFOUT_EN
R8 0 0 0 0 0 0 0 LOGICLK_DIV_PRE 1 LOGIC_EN LOGISYSREFOUT_FMT LOGICLKOUT_FMT
R9 SYSREFREQ_VCM SYNC_EN LOGICLK_DIV_PD LOGICLK_DIV_BYPASS 0 LOGICLK_DIV
R11 rb_CLKPOS
R12 rb_CLKPOS[31:16]
R13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYSREFREQ_DELAY_STEPSIZE
R14 0 0 0 0 0 0 0 SYNC_MUTE_PD 0 0 0 0 0 CLKPOS_CAPTURE_EN SYSREFREQ_MODE SYSREFREQ_LATCH
R15 0 0 0 0 SYSREF_DIV_PRE 1 SYSREF_SP_EN SYSREF_EN SYSREFREQ_DELAY_STEP SYSREFREQ_CLR
R16 SYSREF_PULSE_COUNT SYSREF_DIV
R17 0 0 0 0 0 SYSREF0_DELAY_I SYSREF0_DELAY_PHASE SYSREF_MODE
R18 SYSREF1_DELAY_I SYSREF1_DELAY_PHASE SYSREF0_DELAY_Q
R19 SYSREF2_DELAY_I SYSREF2_DELAY_PHASE SYSREF1_DELAY_Q
R20 SYSREF3_DELAY_I SYSREF3_DELAY_PHASE SYSREF2_DELAY_Q
R21 LOGISYSREF_DELAY_I LOGISYSREF_DELAY_PHASE SYSREF3_DELAY_Q
R22 SYSREF1_DELAY_SCALE SYSREF0_DELAY_SCALE SYSREF_DELAY_DIV 0 0 LOGISYSREF_DELAY_Q
R23 EN_TEMPSENSE 1 MUXOUT_EN 0 0 0 0 0 0 MUXOUT_SEL LOGISYSREF_DELAY_SCALE SYSREF3_DELAY_SCALE SYSREF2_DELAY_SCALE
R24 0 0 0 0 rb_TEMPSENSE EN_TS_COUNT
R25 0 0 0 0 0 0 1 0 0 CLK_DIV_RST CLK_DIV (CLK_MULT) CLK_MUX
R28 0 0 0 FORCE_VCO VCO_SEL 0 0 0 0 0 1 0 0 0
R29 0 0 0 0 0 1 0 1 CAPCTRL
R33 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0
R34 0 0 0 0 0 1 0 0 1 1 0 0 0 1 0 1
R65 0 1 0 0 0 1 0 rb_VCO_SEL 0 0 0 0
R67 0 1 0 1 0 0 0 1 1 1 0 0 1 0 1 1
R72 0 0 0 0 0 0 0 0 0 0 0 0 PULSER_LATCH SYSREFREQ_SPI SYSREF_DELAY_BYPASS
R75 0 0 0 0 0 0 rb_LD 0 0 0 0 0 0 1 1
R79 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0
R86 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
R90 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0