SNAS800 July 2021 LMX1204
The SYSREF outputs within the clock output channels have the same output buffer structure as the clock output buffer, with the inclusion of the common mode adjust field. For the case of the main clocks, the only choice is CML outputs. For the CML outputs, the common mode can be adjusted with the SYSOUTx_VCM field, and the output level is programmable with the SYSOUTx_PWR field. This is to allow DC coupling. This bias adjust is only available on the SYSREF outputs and not the clocks. This is for noise performance reasons.