SNAS800 July   2021 LMX1204

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Range of Dividers and Multiplier
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power On Reset
      2. 7.3.2 Clock Outputs
        1. 7.3.2.1 Clock Output Buffers
        2. 7.3.2.2 Clock MUX
        3. 7.3.2.3 Clock Divider
        4. 7.3.2.4 Clock Multiplier
      3. 7.3.3 SYSREF
        1. 7.3.3.1 SYSREF Output Buffers
          1. 7.3.3.1.1 SYSREF Output Buffer for Main Clocks
          2. 7.3.3.1.2 SYSREF Output Buffer for LOGICLK
        2. 7.3.3.2 SYSREF Frequency and Delay Generation
        3. 7.3.3.3 SYSREFREQ pins
          1. 7.3.3.3.1 SYSREFREQ Pins Common Mode Voltage
          2. 7.3.3.3.2 SYSREFREQ Pin Windowing Feature
        4. 7.3.3.4 SYNC Feature
      4. 7.3.4 LOGICLK Output
        1. 7.3.4.1 LOGICLK Output Format
        2. 7.3.4.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Applications Information
      1. 8.1.1 Current Consumption
      2. 8.1.2 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
    2. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

GUID-20210225-CA0I-5SBR-9JKV-N9P7GTG6VR6B-low.gif Figure 5-1 RHA Package40-Pin VQFNTop View
Table 5-1 Pin Functions
NAME NO. TYPE DESCRIPTION
BIAS01 20 BYP If not using the multiplier, this pin may be left open. If using the multiplier, bypass this pin to GND with a 10-nF capacitor for optimal noise performancer.
BIAS23 31 BYP If not using the multiplier, this pin may be left open. If using the multiplier, bypass this pin to GND with a 10-µF and 0.1-µF capacitor for optimal noise performance.
CLKIN_N 7 I Differential reference input clock. Internal 50-Ω termination. AC-couple with a capacitor appropriate to the input frequency (typically 0.1 µF or smaller). If using single-ended, terminate unused side with external 50-Ω.
CLKIN_P 6
CLKOUT0_N 15 O Differential clock output pairs. Each pin is an open-collector output with internally integrated 50-Ω resistor. AC coupling required.
CLKOUT0_P 14
CLKOUT1_N 19
CLKOUT1_P 18
CLKOUT2_N 32
CLKOUT2_P 33
CLKOUT3_N 36
CLKOUT3_P 37
CS# 10 I SPI chip select. High impedance CMOS input. Accepts up to 3.3 V.
DAP DAP GND Ground these pins.
GND 5,13,17,26,34,38
LOGILKOUT_N 27 O Differential clock output pair. Selectable CML, LVDS, or LVPECL format. Programmable common-mode voltage.
LOGILKOUT_P 28
LOGISYSREFOUT_N 23 O Differential clock output pair. Selectable CML, LVDS, or LVPECL format. External pullup required. Programmable common-mode voltage.
LOGISYSREFOUT_P 24
MUXOUT 1 O Multiplexed pin serial data readback and lock status of the multiplier.
SCK 8 I SPI clock. High impedance CMOS input. Accepts up to 3.3 V.
SDI 9 I SPI data input. High impedance CMOS input. Accepts up to 3.3 V.
SYSREFREQ_N 3 I Differential SYSREF request input for JESD204B support. Internal 50-Ω AC coupled to ground. Supports AC and DC coupling with programmable DC common-mode voltage from 1 V to 2 V.
SYSREFREQ_P 2
SYSREFOUT0_N 12 O Differential SYSREF output pairs. Each pin is an open-collector output with internally integrated 50-Ω resistor and programmable bias level.
SYSREFOUT0_P 11
SYSREFOUT1_N 22
SYSREFOUT1_P 21
SYSREFOUT2_N 29
SYSREFOUT2_P 30
SYSREFOUT3_N 39
SYSREFOUT3_P 40
VCC_CLKIN 4 PWR Connect to a 2.5-V supply. Recommend a shunt high frequency capacitor (typically 0.1 µF or smaller) close to the pin in parallel with larger capacitors (typically 1 µF and 10 µF) farther away.
VCC_LOGICLK 25
VCC01 16
VCC23 35