SNAS800B July   2021  – February 2024 LMX1204

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagram
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
      1. 6.1.1 Range of Dividers and Multiplier
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power On Reset
      2. 6.3.2 Temperature Sensor
      3. 6.3.3 Clock Outputs
        1. 6.3.3.1 Clock Output Buffers
        2. 6.3.3.2 Clock MUX
        3. 6.3.3.3 Clock Divider
        4. 6.3.3.4 Clock Multiplier and Filter Modes
          1. 6.3.3.4.1 General Information About the Clock Multiplier
          2. 6.3.3.4.2 State Machine Clock for the Clock Multiplier
            1. 6.3.3.4.2.1 State Machine Clock
          3. 6.3.3.4.3 Calibration for the Clock Multiplier
          4. 6.3.3.4.4 Using the x1 Clock Multiplier as a Filter
          5. 6.3.3.4.5 Lock Detect for the Clock Multiplier
      4. 6.3.4 Device Functional Modes Configurations
      5. 6.3.5 LOGICLK Output
        1. 6.3.5.1 LOGICLK Output Format
        2. 6.3.5.2 LOGICLK_DIV_PRE and LOGICLK_DIV Dividers
      6. 6.3.6 SYSREF
        1. 6.3.6.1 SYSREF Output Buffers
          1. 6.3.6.1.1 SYSREF Output Buffers for Main Clocks (SYSREFOUT)
          2. 6.3.6.1.2 SYSREF Output Buffer for LOGICLK
        2. 6.3.6.2 SYSREF Frequency and Delay Generation
        3. 6.3.6.3 SYSREFREQ pins and SYSREFREQ_SPI Field
          1. 6.3.6.3.1 SYSREFREQ Pins Common-Mode Voltage
          2. 6.3.6.3.2 SYSREFREQ Windowing Feature
            1. 6.3.6.3.2.1 General Procedure Flowchart for SYSREF Windowing Operation
            2. 6.3.6.3.2.2 SYSREFREQ Repeater Mode With Delay Gen (Retime)
      7. 6.3.7 SYNC Feature
    4. 6.4 Device Functional Modes
  8. 7 Register Map
    1. 7.1 LMX1204 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 SYSREFREQ Input Configuration
      2. 8.1.2 Reducing SYSREF Common Mode Voltages
      3. 8.1.3 Current Consumption
      4. 8.1.4 Treatment of Unused Pins
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1.2 Reducing SYSREF Common Mode Voltages

For DC coupled SYSREF applications, some data converters can require a lower common voltage for the SYSREF outputs than the output can support. For these applications, a resistive divider can be used to reduce the common mode voltage. However, when a path to ground is there, the loading inherently reduces the common mode voltage. For a few test cases, the common mode voltage is measured as shown in.Table 8-1. Note that this table is for the SYSREFOUTx pins, not the LOGISYSREFout pins.
Table 8-1 Impact of Load to GND (Both Pins) on Single-Ended VOD and VCM for SYSREFOUTx_PWR=SYSREFOUTx_VCM=7
Load to GND \VOD VCM VOL
50-Ω 0.72 0.79 0.43
78-Ω 0.86 0.99 0.56
100-Ω 0.96 1.07 0.59
215-Ω 1.13 1.33 0.76
Once the load as seen by the SYSREFOUTx pins is known, the VOD and VCM voltage at those pins can be known. From this point, a resistive divider can be used to create the desired VOD and VCM voltages as shown in Figure 8-6 and Figure 8-7.
GUID-20240124-SS0I-PLMJ-NW9S-2CJ9VBNFG9JM-low.svg Figure 8-6 Reducing VCM With Resistive Dividers (Case 1)
GUID-20240126-SS0I-STQR-HP5J-G5RP3CX2KNVN-low.svg Figure 8-7 Reducing VCM With Resistive Dividers (Case 2)
These examples lead to the calculations in Table 8-2. Note that the resistive divider reduces the VOD, VCM, and ∆VCM (typical variation in VCM).
Table 8-2 Calculated Voltage Values
Where Measured Parameter ADC12DJ5200 AFE7950
At LMX1204 RLoad (Ω) 100 215
VOD (V) 0.96 1.13
VCM 1.065 1.328
∆VCM 0.2 0.2
External Resistors R1(Ω) 60 100
R2 (Ω) 200 115
At Data Converter R3 (Ω) 50 None
Rp (Ω) None 300
R2 || R3 (Ω) 40 None
2R2 || Rp(Ω) 200 130.1887
VOD Ratio 0.4 0.394286
VCM Ratio 0.4 0.534884
Critical Voltages at Data Converter VID (V) 0.384 0.445543
VCM (V) 0.426 0.710326
∆VCM (V) 0.08 0.106977