SBOS487B June 2009 – March 2020 PGA280
01T0 aaaa dddd dddd: Write
Write 'dddd dddd' to internal PGA280 register at address aaaa
1000 aaaa 0000 0000: Read
Read from specified internal PGA280 register at address aaaa [no BUFT on read]. The number of trailing zeros provides the clock for reading data. 16 SCLK pulses are required when reading the data byte plus checksum.
11T0 0ccc: Direct CS Command
Controls CS to pin (all pins are CS-capable, but not simultaneously; only one at a time) for ccc = 0 to 6, corresponding to GPIO0 to GPIO6, if CS mode is activated.
Within the command byte, T = 1 triggers the current buffer (BUF). Each command is terminated with setting CS to high; commands can be chained within a period of CS active low, but require a checksum byte, or a dummy byte when checksum mode is disabled.
BUF cannot be triggered during a read command.
Here are several examples (discrete commands):
Read Register 3:
Send 0x8300; response: 0xzz19 (this value is the initial setting of BUFTIM).
The first byte zz contains the line state (3-state) of SDO. The second byte is data.
The PGA280 sends the CHKsum, if clocks are available while CS: Send 0x830000. Response: 0xzz1937
Write Register 0:
Send 0x4018; set gain to 1V/V.
Write Register 4:
Send 0x44FF; reset all error flags.
Read Register 4:
Send 0x8400; response: 0xzz00 (no error flags set).