SBOS487B June   2009  – March 2020 PGA280

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Electrical Characteristics
    3. 6.3 Timing Requirements: Serial Interface
    4. 6.4 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Functional Blocks
        1. 7.3.1.1 Input Switch Network
        2. 7.3.1.2 Input Amplifier, Gain Network, and Buffer
        3. 7.3.1.3 Current Buffer
        4. 7.3.1.4 Input Protection
        5. 7.3.1.5 EMI Susceptibility
        6. 7.3.1.6 Output Stage
        7. 7.3.1.7 Output Filter
        8. 7.3.1.8 Single-Ended Output
        9. 7.3.1.9 Error Detection
      2. 7.3.2 Error Indicators
        1. 7.3.2.1 Input Clamp Conduction (ICAerr)
        2. 7.3.2.2 Input Overvoltage (IOVerr)
        3. 7.3.2.3 Gain Network Overload (GAINerr)
        4. 7.3.2.4 Output Amplifier (OUTerr)
        5. 7.3.2.5 CheckSum Error (CRCerr)
    4. 7.4 Device Functional Modes
      1. 7.4.1 GPIO Operation Mode
        1. 7.4.1.1 CS Mode
    5. 7.5 Programming
      1. 7.5.1 SPI and Register Description
      2. 7.5.2 Command Structure and Register Overview
        1. 7.5.2.1 Command Byte
        2. 7.5.2.2 Extended CS
          1. 7.5.2.2.1 SPI Timing Diagrams (Read and Write)
          2. 7.5.2.2.2 GPIO Pin Reference
          3. 7.5.2.2.3 Checksum
      3. 7.5.3 GPIO Configuration
      4. 7.5.4 Buffer Timing
    6. 7.6 Register Map
      1. 7.6.1  Register 0: Gain and External MUX Address (address = 00h) [reset = 0000 0000b]
      2. 7.6.2  Register 1: Software Reset Register (address = 01h) [reset = 0000 0000b]
      3. 7.6.3  Register 2: SPI: MODE Selection to GPIO-Pin (address = 02h) [reset = 0000 0000b]
      4. 7.6.4  Register 3: BUF Timeout Register (address = 03h) [reset = 0001 1001b]
      5. 7.6.5  Register 4: Error Register (address = 04h) [reset = 0000 0000b]
      6. 7.6.6  Register 5: GPIO Register (address = 05h) [reset = 0000 0000b]
      7. 7.6.7  Register 6: Input Switch Control Register 1 (address = 06h) [reset = 0110 0000b]
      8. 7.6.8  Register 7: Input Switch Control Register 2 (address =07h ) [reset = 0000 0000b]
      9. 7.6.9  Register 8: GPIO Configuration Register (address = 08h) [reset = 0000 0000b]
      10. 7.6.10 Register 9: CS Configuration Mode Register (address = 09h) [reset = 0000 0000b]
      11. 7.6.11 Register 10: Configuration Register 1 (address = 0Ah) [reset = 0000 0000b]
      12. 7.6.12 Register 11: Configuration Register 2 (address = 0Bh) [reset = 0001 0000b]
      13. 7.6.13 Register 12: Special Functions Register (address = 0Ch) [reset = 0000 0000b]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Clock Synchronization
      2. 8.1.2 Quiescent Current
      3. 8.1.3 Settling Time
      4. 8.1.4 Overload Recovery
  9. 9 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.2.2.3 Checksum

SPI communication can be secured by adding a checksum byte to the write and read data. If this mode is activated by setting CHKsumE (bit 0 in Register 11), the PGA280 expects a valid checksum; otherwise, the device ignores the received data and sets CHKerr in Register 4. This event may require a Register 4 read after each write completes. The PGA280 always responds to a read with checksum if sufficient SCLK pulses (16) are provided after the command byte.

A straight checksum (ignore carry) with a starting value of 0x9B, an 8-bit byte, is used. Polynomial value: 1001 1010b = 0x9B (b denotes binary, 0x denotes hex coding)

Write to device: Command byte + Data byte + CHKsum byte

CHKsum = Polynomial value + Command byte + Data byte*;

Read command to device = Command byte + CHKsum byte

Response: Data byte + CHKsum byte

CHKsum = Polynomial value + Command byte + Data byte

*The command for activating the CS on a GPIO pin (after configuration) is only a command byte: 11Tx 0ccc.

Example: 0xC15C. This instruction activates CS on GPIO1. The 5C is the checksum [(0x9B + 0xC1) mod 0x100 = 0x5C]

The checksum is calculated only for the communication to or from the PGA280. In extended SPI mode, if connecting the CS (ECS) for other SPI devices to the PGA280 port, the external device has to provide its own checksum character, if available.

Examples:

0x4101DD Send Reset [CHKsum calculation: (0x9B + 0x41 + 0x01) mod 0x100 = 0xDD]

0x4B11F7 Activate CHKsum bit 0 of Register 11. Note that activation of the CHK bit requires proper Checksum.

0x8B260000 Read Configuration Register 11 (contains 0x11) [0x9B + 0x8B = 0x26]

0x1137 Response includes the CHKsum [0x9B + 0x8B + 0x11 = 0x37]

0x44FFDF Reset all error flags in Register 4 [0x9B + 0x44 + 0xFF = 0xDF]

0x841F0000 Read Register 4 [0x9B + 0x84 = 0x1F]

0x001F No errors indicated if 00 [0x9B + 0x84 + 0x00 = 0x1F]

Commands can be chained while CS is active low; all bytes are added for checksum:

Examples:

0x4C 07 EE; Activate MUX0, MUX1, and MUX2 to GPIO0, GPIO1, and GPIO2, respectively

0x64 FF FE 40 1B 59 80 D9 00 00; Write to Register 4 with BUF trigger and reset all error flags

: Write to Register 0 and set gain 1 V/V; MUX0 and MUX1 set high

: Read Register 0, provide 16 SCLKs