SBOS487B June 2009 – March 2020 PGA280
SPI communication can be secured by adding a checksum byte to the write and read data. If this mode is activated by setting CHKsumE (bit 0 in Register 11), the PGA280 expects a valid checksum; otherwise, the device ignores the received data and sets CHKerr in Register 4. This event may require a Register 4 read after each write completes. The PGA280 always responds to a read with checksum if sufficient SCLK pulses (16) are provided after the command byte.
A straight checksum (ignore carry) with a starting value of 0x9B, an 8-bit byte, is used. Polynomial value: 1001 1010b = 0x9B (b denotes binary, 0x denotes hex coding)
Write to device: Command byte + Data byte + CHKsum byte
CHKsum = Polynomial value + Command byte + Data byte*;
Read command to device = Command byte + CHKsum byte
Response: Data byte + CHKsum byte
CHKsum = Polynomial value + Command byte + Data byte
*The command for activating the CS on a GPIO pin (after configuration) is only a command byte: 11Tx 0ccc.
Example: 0xC15C. This instruction activates CS on GPIO1. The 5C is the checksum [(0x9B + 0xC1) mod 0x100 = 0x5C]
The checksum is calculated only for the communication to or from the PGA280. In extended SPI mode, if connecting the CS (ECS) for other SPI devices to the PGA280 port, the external device has to provide its own checksum character, if available.
0x4101DD Send Reset [CHKsum calculation: (0x9B + 0x41 + 0x01) mod 0x100 = 0xDD]
0x4B11F7 Activate CHKsum bit 0 of Register 11. Note that activation of the CHK bit requires proper Checksum.
0x8B260000 Read Configuration Register 11 (contains 0x11) [0x9B + 0x8B = 0x26]
0x1137 Response includes the CHKsum [0x9B + 0x8B + 0x11 = 0x37]
0x44FFDF Reset all error flags in Register 4 [0x9B + 0x44 + 0xFF = 0xDF]
0x841F0000 Read Register 4 [0x9B + 0x84 = 0x1F]
0x001F No errors indicated if 00 [0x9B + 0x84 + 0x00 = 0x1F]
Commands can be chained while CS is active low; all bytes are added for checksum:
0x4C 07 EE; Activate MUX0, MUX1, and MUX2 to GPIO0, GPIO1, and GPIO2, respectively
0x64 FF FE 40 1B 59 80 D9 00 00; Write to Register 4 with BUF trigger and reset all error flags
: Write to Register 0 and set gain 1 V/V; MUX0 and MUX1 set high
: Read Register 0, provide 16 SCLKs