SBOS487B June 2009 – March 2020 PGA280
LTD: Individual error signals are not latched if this bit is set to 1. With EFout activated on GPIO3, the error condition can be observed in real time, but error suppression time is applied. Clear errors in Register 4 after writing 1 to this bit.
FLAGTIM0 to 3: Choose the number of clock cycles (nominally 1 MHz) according to Table 3 for suppression of the error flags in Register 4. The timeout starts after the end of BUFA. Alternatively, the timeout can start with the event if the buffer is not active or Register 10, bit 3 is set high. Allow delayed activation for the individual error sources in the microsecond range.
CHKsumE: Checksum is enabled by writing a 1 to bit 0. A correct checksum is always required for enabling. After this bit is set, all communication to the device requires a valid checksum, until 0 is written to this bit. Alternatively, a software reset [0x4101DD] or power-on reset can be performed to reset this function.
|FLGTIM [3:0]||CLOCK CYCLES(1)|