SBOS487B June   2009  – March 2020 PGA280

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Electrical Characteristics
    3. 6.3 Timing Requirements: Serial Interface
    4. 6.4 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Functional Blocks
        1. 7.3.1.1 Input Switch Network
        2. 7.3.1.2 Input Amplifier, Gain Network, and Buffer
        3. 7.3.1.3 Current Buffer
        4. 7.3.1.4 Input Protection
        5. 7.3.1.5 EMI Susceptibility
        6. 7.3.1.6 Output Stage
        7. 7.3.1.7 Output Filter
        8. 7.3.1.8 Single-Ended Output
        9. 7.3.1.9 Error Detection
      2. 7.3.2 Error Indicators
        1. 7.3.2.1 Input Clamp Conduction (ICAerr)
        2. 7.3.2.2 Input Overvoltage (IOVerr)
        3. 7.3.2.3 Gain Network Overload (GAINerr)
        4. 7.3.2.4 Output Amplifier (OUTerr)
        5. 7.3.2.5 CheckSum Error (CRCerr)
    4. 7.4 Device Functional Modes
      1. 7.4.1 GPIO Operation Mode
        1. 7.4.1.1 CS Mode
    5. 7.5 Programming
      1. 7.5.1 SPI and Register Description
      2. 7.5.2 Command Structure and Register Overview
        1. 7.5.2.1 Command Byte
        2. 7.5.2.2 Extended CS
          1. 7.5.2.2.1 SPI Timing Diagrams (Read and Write)
          2. 7.5.2.2.2 GPIO Pin Reference
          3. 7.5.2.2.3 Checksum
      3. 7.5.3 GPIO Configuration
      4. 7.5.4 Buffer Timing
    6. 7.6 Register Map
      1. 7.6.1  Register 0: Gain and External MUX Address (address = 00h) [reset = 0000 0000b]
      2. 7.6.2  Register 1: Software Reset Register (address = 01h) [reset = 0000 0000b]
      3. 7.6.3  Register 2: SPI: MODE Selection to GPIO-Pin (address = 02h) [reset = 0000 0000b]
      4. 7.6.4  Register 3: BUF Timeout Register (address = 03h) [reset = 0001 1001b]
      5. 7.6.5  Register 4: Error Register (address = 04h) [reset = 0000 0000b]
      6. 7.6.6  Register 5: GPIO Register (address = 05h) [reset = 0000 0000b]
      7. 7.6.7  Register 6: Input Switch Control Register 1 (address = 06h) [reset = 0110 0000b]
      8. 7.6.8  Register 7: Input Switch Control Register 2 (address =07h ) [reset = 0000 0000b]
      9. 7.6.9  Register 8: GPIO Configuration Register (address = 08h) [reset = 0000 0000b]
      10. 7.6.10 Register 9: CS Configuration Mode Register (address = 09h) [reset = 0000 0000b]
      11. 7.6.11 Register 10: Configuration Register 1 (address = 0Ah) [reset = 0000 0000b]
      12. 7.6.12 Register 11: Configuration Register 2 (address = 0Bh) [reset = 0001 0000b]
      13. 7.6.13 Register 12: Special Functions Register (address = 0Ch) [reset = 0000 0000b]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Clock Synchronization
      2. 8.1.2 Quiescent Current
      3. 8.1.3 Settling Time
      4. 8.1.4 Overload Recovery
  9. 9 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Typical Characteristics

At TA = +25°C, VSP = +15V, VSN = –15V, VSON = 0V, VSOP = 5V, DVDD = +3V, DGND = 0V, RL = 2.5kΩ to VSOP/2 = VOCM, G = 1V/V, using internal clock, BUF inactive, VCM = 0V, and differential input and output, unless otherwise noted.
PGA280 tc_vos_histo_g128_bos487.gifFigure 2. Offset Voltage Production Distribution (G = 128)
PGA280 tc_vos_drift_histo_g128_bos487.gifFigure 4. Offset Voltage Drift Distribution (G = 128)
PGA280 tc_cmrr_histo_g128_bos487.gifFigure 6. Common-Mode Rejection Distribution (G = 128)
PGA280 tc_gain_er_histo_g128_bos487.gifFigure 8. Gain-Error Distribution (G = 128)
PGA280 tc_gain_er_gain_set_bos487.gif
Figure 10. Gain Error vs Gain Setting
PGA280 tc_max_gain_er_seq_gain_bos487.gifFigure 12. Maximum Gain-Error Deviation Between
Sequential Gain Settings (Mean With ±3 σ)
PGA280 tc_psrr_fqcy_bos487.gif
Figure 14. Power-Supply Rejection vs Frequency
PGA280 tc_inref_noise_spec_bos487.gif
Figure 16. Input-Referred Noise Spectrum
PGA280 tc_vin_limit_temp_bos487.gif
Figure 18. Input Voltage Range Limits vs Temperature
PGA280 tc_in_ibias_histo_g128_bos487.gifFigure 20. Input Bias Current Distribution (G = 128)
PGA280 tc_in_ioffset_histo_g1_128_bos487.gifFigure 22. Input Offset Current Distribution (G = 1, G = 128)
PGA280 tc_iq_vsp_vsop_temp_bos487.gifFigure 24. Quiescent Current From Supplies (VSP and VSOP) vs Temperature
PGA280 tc_gain_nl_cal_g1_bos487.gif
Figure 26. Gain Nonlinearity With End-Point Calibration
(G = 1)
PGA280 tc_pos_iout_lim_histo_bos487.gif
Figure 28. Positive Output Current Limit Distribution
PGA280 tc_iout_lim_temp_bos487.gif
Figure 30. Output Current Limit vs Temperature
PGA280 tc_switch_on_series_in_vcm_bos487.gifFigure 32. Switch-On Resistance
and Series Input Resistance
vs Common-Mode Voltage at Various Supply Voltages
PGA280 tc_wirebreak_histo_bos487.gifFigure 34. Wire Break Current Distribution
PGA280 tc_ext_clk_fqcy_vos_histo_g128_bos487.gifFigure 36. Influence of External Clock Frequency to
VOS Performance (G = 128)
PGA280 tc_step_resp_g128_bos487.gif
Figure 38. Step Response (G = 128)
PGA280 tc_step_resp_g1_bos487.gif
Figure 40. Step Response (G = 1)
PGA280 tc_freq_osc_temp_bos487.gif
Figure 42. Oscillator Frequency vs
Temperature
PGA280 tc_vos_histo_g1_bos487.gifFigure 3. Offset Voltage Production Distribution (G = 1)
PGA280 tc_vos_drift_histo_g1_bos487.gifFigure 5. Offset Voltage Drift Distribution (G = 1)
PGA280 tc_cmrr_histo_g1_bos487.gifFigure 7. Common-Mode Rejection Distribution (G = 1)
PGA280 tc_gain_er_histo_g1_bos487.gifFigure 9. Gain-Error Distribution (G = 1)
PGA280 tc_gain_err_drift_gain_set_bos487.gifFigure 11. Gain-Error Drift Distribution
vs Gain Setting (Mean With ±3 σ)
PGA280 tc_gain_er_dist_gain_set_bos487.gif
Figure 13. Gain-Error Distribution vs
Gain Setting (Mean With ±3σ)
PGA280 tc_cmrr_fqcy_bos487.gif
Figure 15. Common-Mode Rejection vs Frequency
PGA280 tc_sm_signal_gain_fqcy_bos487.gif
Figure 17. Small-Signal Gain vs Frequency
PGA280 tc_ibias_gain_set_bos487.gif
Figure 19. Bias Current vs Gain Setting
PGA280 tc_in_ibias_histo_g1_bos487.gifFigure 21. Input Bias Current Distribution (G = 1)
PGA280 tc_in_ibias_ioffset_temp_bos487.gif
Figure 23. Input Bias Current and Input Offset Current
vs Temperature
PGA280 tc_idvdd_spi_temp_bos487.gifFigure 25. Digital Supply Current
With and Without SPI Communication
vs Temperature
PGA280 tc_gain_nl_temp_bos487.gif
Figure 27. Gain Nonlinearity vs Temperature
PGA280 tc_neg_iout_lim_histo_bos487.gif
Figure 29. Negative Output Current Limit Distribution
PGA280 tc_out_swing_temp_bos487.gif
Figure 31. Output Swing To Rail vs Temperature
(VSOP – VSON = 5 V)
PGA280 tc_switch_on_series_in_temp_bos487.gifFigure 33. Switch-On Resistance
and Series Input Resistance
vs Temperature
PGA280 tc_wirebreak_temp_bos487.gif
Figure 35. Wire Break Current Magnitude vs Temperature
PGA280 tc_ext_clk_fqcy_vos_histo_g1_bos487.gifFigure 37. Influence of External Clock Frequency to
VOS Performance (G = 1)
PGA280 tc_step_resp_g8_bos487.gif
Figure 39. Step Response (G = 8)
PGA280 tc_output_overload_bos487.gif
Figure 41. Output Overload Recovery
PGA280 tc_in_buf_voffset_histo_bos487.gifFigure 43. Input Current Buffer Offset Voltage Distribution