SBOS487B June   2009  – March 2020 PGA280

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Electrical Characteristics
    3. 6.3 Timing Requirements: Serial Interface
    4. 6.4 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Functional Blocks
        1. 7.3.1.1 Input Switch Network
        2. 7.3.1.2 Input Amplifier, Gain Network, and Buffer
        3. 7.3.1.3 Current Buffer
        4. 7.3.1.4 Input Protection
        5. 7.3.1.5 EMI Susceptibility
        6. 7.3.1.6 Output Stage
        7. 7.3.1.7 Output Filter
        8. 7.3.1.8 Single-Ended Output
        9. 7.3.1.9 Error Detection
      2. 7.3.2 Error Indicators
        1. 7.3.2.1 Input Clamp Conduction (ICAerr)
        2. 7.3.2.2 Input Overvoltage (IOVerr)
        3. 7.3.2.3 Gain Network Overload (GAINerr)
        4. 7.3.2.4 Output Amplifier (OUTerr)
        5. 7.3.2.5 CheckSum Error (CRCerr)
    4. 7.4 Device Functional Modes
      1. 7.4.1 GPIO Operation Mode
        1. 7.4.1.1 CS Mode
    5. 7.5 Programming
      1. 7.5.1 SPI and Register Description
      2. 7.5.2 Command Structure and Register Overview
        1. 7.5.2.1 Command Byte
        2. 7.5.2.2 Extended CS
          1. 7.5.2.2.1 SPI Timing Diagrams (Read and Write)
          2. 7.5.2.2.2 GPIO Pin Reference
          3. 7.5.2.2.3 Checksum
      3. 7.5.3 GPIO Configuration
      4. 7.5.4 Buffer Timing
    6. 7.6 Register Map
      1. 7.6.1  Register 0: Gain and External MUX Address (address = 00h) [reset = 0000 0000b]
      2. 7.6.2  Register 1: Software Reset Register (address = 01h) [reset = 0000 0000b]
      3. 7.6.3  Register 2: SPI: MODE Selection to GPIO-Pin (address = 02h) [reset = 0000 0000b]
      4. 7.6.4  Register 3: BUF Timeout Register (address = 03h) [reset = 0001 1001b]
      5. 7.6.5  Register 4: Error Register (address = 04h) [reset = 0000 0000b]
      6. 7.6.6  Register 5: GPIO Register (address = 05h) [reset = 0000 0000b]
      7. 7.6.7  Register 6: Input Switch Control Register 1 (address = 06h) [reset = 0110 0000b]
      8. 7.6.8  Register 7: Input Switch Control Register 2 (address =07h ) [reset = 0000 0000b]
      9. 7.6.9  Register 8: GPIO Configuration Register (address = 08h) [reset = 0000 0000b]
      10. 7.6.10 Register 9: CS Configuration Mode Register (address = 09h) [reset = 0000 0000b]
      11. 7.6.11 Register 10: Configuration Register 1 (address = 0Ah) [reset = 0000 0000b]
      12. 7.6.12 Register 11: Configuration Register 2 (address = 0Bh) [reset = 0001 0000b]
      13. 7.6.13 Register 12: Special Functions Register (address = 0Ch) [reset = 0000 0000b]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Clock Synchronization
      2. 8.1.2 Quiescent Current
      3. 8.1.3 Settling Time
      4. 8.1.4 Overload Recovery
  9. 9 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Register Map

Table 1. Register Map(1)

REGISTER
(Decimal, [Hex])(4) 		aaaa
(Binary)		 R/W B7 B6 B5 B4 B3 B2 B1 B0 DESCRIPTION RESET VALUES(2)
0 0000 W/R G4 G3 G2 G1 G0 MUX2 MUX1 MUX0 Gain and optional MUX register 0000 0000b
1 0001 W SftwrRstNote2x Write-only register, soft reset, write 1 0000 0000b
2 0010 W/R CP6 CP5 CP4 CP3 CP2 CP1 CP0 SPI-MODE selection to GPIO-pin 0000 0000b
3 0011 W/R BUFTIM5 BUFTIM4 BUFTIM3 BUFTIM2 BUFTIM1 BUFTIM0 Set BUF time-out 0001 1001b
4 0100 W/R CHKerr IARerr BUFA ICAerr EF OUTerr GAINerr IOVerr Error Register; reset error bit: write 1 0000 0000b
5 0101 W/R GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIO Register Data force out or sense 0000 0000b
6 0110 W/R SW-A1 SW-A2 SW-B1 SW-B2 SW-C1 SW-C2 SW-D12 Input switch control 1 0110 0000b
7 0111 W/R SW-F1 SW-F2 SW-G1 SW-G2 Input switch control 2 0000 0000b
8 1000 W/R DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0 Configure pin to out = 1 or in = 0 0000 0000b
9 1001 W/R ECS6 ECS5 ECS4 ECS3 ECS2 ECS1 ECS0 Extended CS mode (1 = enable) 0000 0000b
10 [A] 1010 W/R MUX-D dis IARerr dis BUFAPol at pin ICAerr dis ED BUFA suppress OUTerr dis GAINerr dis IOVerr dis Various configuration settings 0000 0000b
11 [B] 1011 W/R LTD FLGTIM3 FLGTIM2 FLGTIM1 FLGTIM0 Reserved CHKsumE Various configuration settings 0001 0000b
12 [C] 1100 W/R OSCout SYNCin BUFAout BUFTin EFout MUX2 MUX1 MUX0 Special function register 0000 0000b
PIN GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 Register bit reference to GPIO pin(3)
(1) Blank register bits are ignored and undefined.
(2) Power-on reset values are SftwrRst values.
(3) Details for GPIO pin assignments are shown in Figure 54.
(4) Registers 13 to 15 are for test purposes; read-only.