SBOS487B June   2009  – March 2020 PGA280

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Electrical Characteristics
    3. 6.3 Timing Requirements: Serial Interface
    4. 6.4 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Functional Blocks
        1. 7.3.1.1 Input Switch Network
        2. 7.3.1.2 Input Amplifier, Gain Network, and Buffer
        3. 7.3.1.3 Current Buffer
        4. 7.3.1.4 Input Protection
        5. 7.3.1.5 EMI Susceptibility
        6. 7.3.1.6 Output Stage
        7. 7.3.1.7 Output Filter
        8. 7.3.1.8 Single-Ended Output
        9. 7.3.1.9 Error Detection
      2. 7.3.2 Error Indicators
        1. 7.3.2.1 Input Clamp Conduction (ICAerr)
        2. 7.3.2.2 Input Overvoltage (IOVerr)
        3. 7.3.2.3 Gain Network Overload (GAINerr)
        4. 7.3.2.4 Output Amplifier (OUTerr)
        5. 7.3.2.5 CheckSum Error (CRCerr)
    4. 7.4 Device Functional Modes
      1. 7.4.1 GPIO Operation Mode
        1. 7.4.1.1 CS Mode
    5. 7.5 Programming
      1. 7.5.1 SPI and Register Description
      2. 7.5.2 Command Structure and Register Overview
        1. 7.5.2.1 Command Byte
        2. 7.5.2.2 Extended CS
          1. 7.5.2.2.1 SPI Timing Diagrams (Read and Write)
          2. 7.5.2.2.2 GPIO Pin Reference
          3. 7.5.2.2.3 Checksum
      3. 7.5.3 GPIO Configuration
      4. 7.5.4 Buffer Timing
    6. 7.6 Register Map
      1. 7.6.1  Register 0: Gain and External MUX Address (address = 00h) [reset = 0000 0000b]
      2. 7.6.2  Register 1: Software Reset Register (address = 01h) [reset = 0000 0000b]
      3. 7.6.3  Register 2: SPI: MODE Selection to GPIO-Pin (address = 02h) [reset = 0000 0000b]
      4. 7.6.4  Register 3: BUF Timeout Register (address = 03h) [reset = 0001 1001b]
      5. 7.6.5  Register 4: Error Register (address = 04h) [reset = 0000 0000b]
      6. 7.6.6  Register 5: GPIO Register (address = 05h) [reset = 0000 0000b]
      7. 7.6.7  Register 6: Input Switch Control Register 1 (address = 06h) [reset = 0110 0000b]
      8. 7.6.8  Register 7: Input Switch Control Register 2 (address =07h ) [reset = 0000 0000b]
      9. 7.6.9  Register 8: GPIO Configuration Register (address = 08h) [reset = 0000 0000b]
      10. 7.6.10 Register 9: CS Configuration Mode Register (address = 09h) [reset = 0000 0000b]
      11. 7.6.11 Register 10: Configuration Register 1 (address = 0Ah) [reset = 0000 0000b]
      12. 7.6.12 Register 11: Configuration Register 2 (address = 0Bh) [reset = 0001 0000b]
      13. 7.6.13 Register 12: Special Functions Register (address = 0Ch) [reset = 0000 0000b]
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Clock Synchronization
      2. 8.1.2 Quiescent Current
      3. 8.1.3 Settling Time
      4. 8.1.4 Overload Recovery
  9. 9 Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.2 Electrical Characteristics

at TA = 25°C, VSP = 15 V, VSN = –15 V, VSON = 0 V, VSOP = 5 V, DVDD = 3 V, DGND = 0 V, RL = 2.5 kΩ to VSOP/2 = VOCM, G = 1 V/V, using internal clock, BUF inactive, VCM = 0 V, and differential input and output (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
VOS Offset voltage, RTI(1) Gain = 1 V/V, 1.375 V/V ±50 ±250 µV
Gain = 128 V/V ±3 ±15
dVOS/dT vs temperature(2) TA = –40°C to +105°C Gain = 1 V/V ±0.2 ±0.6 μV/°C
Gain = 128 V/V ±0.03 ±0.17
PSR vs power supply, RTI VSP – VSN = 10 V and 36 V,
gain = 1 V/V, 128 V/V		 ±0.3 ±3 µV/V
dVOS/df vs external clock, RTI(4) 0.8 MHz to 1.2 MHz, gain = 1 V/V ±0.05 μV/kHz
0.8 MHz to 1.2 MHz, gain = 128 V/V ±0.001
Long-term stability(5) Gain = 128 V/V 3.5 nV/month
Input impedance Single-ended and differential > 1 GΩ
Input capacitance, IN1 / IN2 Single-ended 12 / 8 pF
Input voltage Gain = 1 V/V, gain = 128 V/V, TA = –40°C to +105°C (VSN) + 2.5 (VSP) – 2.5 V
CMR Common-mode rejection, RTI Gain = 1 V/V ±0.3 ±3 μV/V
Gain = 128 V/V ±0.08 ±0.8
Gain = 128 V/V, TA = –40°C to +105°C ±0.1 ±1.5
SINGLE-ENDED OUTPUT CONNECTION
VOS Offset voltage, RTI, SE out Gain = 1 V/V, 1.375 V/V, SE ±120 μV
Gain = 1V/V ±3
dVOS/dT vs temperature, SE out Gain = 1 V/V, SE, TA = –40°C to +105°C 0.6 μV/°C
Gain = 64 V/V, SE, TA = –40°C to +105°C 0.05
INPUT BIAS CURRENT(4)
IB Bias current Gain = 1 V/V ±0.3 ±1 nA
Gain = 128 V/V ±0.8 ±2
Gain = 1 V/V, gain = 128 V/V, TA = –40°C to +105°C ±0.6 ±2
IOS Offset current Gain = 1 V/V, gain = 128 V/V ±0.1 ±0.5 nA
Gain = 1 V/V, gain = 128 V/V, TA = –40°C to +105°C ±0.9 ±2
NOISE
eNI Voltage noise, RTI; target f = 0.01 Hz to 10 Hz RS = 0 Ω, G = 128 V/V 420 nVPP
RS = 0 Ω, G = 1 V/V 4.5 μVPP
f = 1 kHz RS = 0 Ω, G = 128 V/V 22 nV/√Hz
RS = 0 Ω, G = 1 V/V 240 nV/√Hz
IN Current noise, RTI f = 0.01 Hz to 10 Hz RS = 10 MΩ, G = 128 V/V 1.7 pAPP
f = 1 kHz RS = 10 MΩ, G = 128 V/V 90 fA/√Hz
GAIN (Output Swing = ±4.5 V)(6)
Range of input gain ⅛ to 128 V/V
Range of output gain 1 and 1⅜ V/V
Gain error, all binary steps All gains ±0.03 ±0.15 %
vs temperature(2)(7) No load, all gains except G = 128 V/V, TA = –40°C to +105°C –0.5 ±2 ppm/°C
No load, G = 128 V/V, TA = –40°C to +105°C –1 ±3 ppm/°C
Gain step matching(4) (gain to gain) No load, all gains See
Nonlinearity No load, all gains(3) 1.5 10 ppm
Nonlinearity over temperature(2) No load, all gains, TA = –40°C to +105°C 3 ppm
OUTPUT
Voltage output swing from rail(4) TA = –40°C to +105°C VSOP = 5 V,
load current 2 mA		 40 100 mV
VSOP = 2.7 V,
load current 1.5 mA		 100 mV
Capacitive load drive 500 pF
ISC Short-circuit current To VSOP/2, gain = 1.375 V/V 7 15 25 mA
Output resistance Each output VOP and VON 200 mΩ
VOCM
VOCM supply voltage VSP – 2 V > VOCM, TA = –40°C to +105°C (VSON) + 0.1 (VSOP) – 0.1 V
IB Bias current into VOCM 3 100 nA
VOCM input resistance 1 GΩ
INTERNAL OSCILLATOR
Frequency of internal clock(2)(4) 0.8 1 1.2 MHz
Ext. oscillator frequency 0.8 1 1.2 MHz
FREQUENCY RESPONSE
GBP Gain bandwidth product(4) G > 4 6 MHz
SR Slew rate(4), 4-VPP output step G = 1, CL = 100 pF, BUF On 1 V/μs
G = 8, CL = 100 pF 2 V/μs
G = 128, CL = 100 pF 1 V/μs
tS Settling time(4) To 0.01% G = 8, VO = 8-VPP step 20 μs
G = 128, VO = 8-VPP step 40 μs
To 0.001% G = 8, VO = 8-VPP step 30 μs
G = 128, VO = 8-VPP step 40 μs
Overload recovery, input(4) 0.5 V over supply, G = ⅛ to 128 8 μs
Overload recovery, output(4) ±5.5-VP input, G = 1 V/V 6 μs
INPUT MULTIPLEXER (Two-Channel)
Crosstalk, INP1 to INP2 At dc, gain = 128 V/V < –130 dB
Series-resistance(4)—see Figure 44 600 Ω
Switch on-resistance(4) 450 Ω
Current source and sink(4) To GND 70 95 125 μA
INPUT CURRENT BUFFER (BUF)
VOS Offset voltage(4) Buffer active 15 mV
DIGITAL I/O (Supply: 2.7 V to 5.5 V)
Input (logic low threshold) 0 (DVDD)x0.2 V
Input (logic high threshold) 0.8x(DVDD) DVDD V
Output (logic low) IOUT = 4 mA, sink 0.7 V
Output (logic high) IOUT = 2 mA, source DVDD – 0.5 V
SCLK, frequency 10 MHz
POWER SUPPLY: Input Stage (VSN – VSP)
Specified voltage TA = –40°C to +105°C 10 36 V
Operating voltage 10 to 38 V
IQ Quiescent current TA = –40°C to +105°C VSP 2.4 3 mA
VSN 2.1 3 mA
POWER SUPPLY: Output Stage (VSOP – VSON)
Specified voltage VSP – 1.5 V ≥ VSOP, TA = –40°C to +105°C 2.7 5.5 V
Voltage for VSOP, upper limit (VSP – 2 V) > VOCM, (VSP – 5 V) > VSON (VSP) V
Voltage for VSON (VSP – 2 V) > VOCM, VSP ≥ VSOP (VSN) to (VSP) – 5 V
IQ Quiescent Current VSOP, TA = –40°C to +105°C 0.75 1 mA
POWER SUPPLY: Digital (DVDD – DGND)
Specified voltage TA = –40°C to +105°C 2.7 5.5 V
Voltage for DVDD, upper limit (VSP) – 1 V
Voltage for DGND, lower limit (VSN) V
IQ Quiescent current(4) Static condition, no external load,
DVDD = 3 V, TA = –40°C to +105°C		 0.07 0.13 mA
TEMPERATURE
Specified temperature –40 105 °C
Operating temperature –55 140 °C
θJA Thermal resistance SSOP, High-K board, JESD51 80 °C/W
(1) RTI: Referred to input.
(2) Specified by design; not production tested.
(3) Only G = 1 is production tested.
(4) See section and typical characteristic graphs.
(5) 300-hour life test at +150°C demonstrated randomly distributed variation in the range of measurement limits.
(6) Gains smaller than ½ are measured with smaller output swing.
(7) See Figure 11 for typical gain error drift of various gain settings.