SBOS487B June   2009  – March 2020 PGA280


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Electrical Characteristics
    3. 6.3 Timing Requirements: Serial Interface
    4. 6.4 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Functional Blocks
        1. Input Switch Network
        2. Input Amplifier, Gain Network, and Buffer
        3. Current Buffer
        4. Input Protection
        5. EMI Susceptibility
        6. Output Stage
        7. Output Filter
        8. Single-Ended Output
        9. Error Detection
      2. 7.3.2 Error Indicators
        1. Input Clamp Conduction (ICAerr)
        2. Input Overvoltage (IOVerr)
        3. Gain Network Overload (GAINerr)
        4. Output Amplifier (OUTerr)
        5. CheckSum Error (CRCerr)
    4. 7.4 Device Functional Modes
      1. 7.4.1 GPIO Operation Mode
        1. CS Mode
    5. 7.5 Programming
      1. 7.5.1 SPI and Register Description
      2. 7.5.2 Command Structure and Register Overview
        1. Command Byte
        2. Extended CS
          1. SPI Timing Diagrams (Read and Write)
          2. GPIO Pin Reference
          3. Checksum
      3. 7.5.3 GPIO Configuration
      4. 7.5.4 Buffer Timing
    6. 7.6 Register Map
      1. 7.6.1  Register 0: Gain and External MUX Address (address = 00h) [reset = 0000 0000b]
      2. 7.6.2  Register 1: Software Reset Register (address = 01h) [reset = 0000 0000b]
      3. 7.6.3  Register 2: SPI: MODE Selection to GPIO-Pin (address = 02h) [reset = 0000 0000b]
      4. 7.6.4  Register 3: BUF Timeout Register (address = 03h) [reset = 0001 1001b]
      5. 7.6.5  Register 4: Error Register (address = 04h) [reset = 0000 0000b]
      6. 7.6.6  Register 5: GPIO Register (address = 05h) [reset = 0000 0000b]
      7. 7.6.7  Register 6: Input Switch Control Register 1 (address = 06h) [reset = 0110 0000b]
      8. 7.6.8  Register 7: Input Switch Control Register 2 (address =07h ) [reset = 0000 0000b]
      9. 7.6.9  Register 8: GPIO Configuration Register (address = 08h) [reset = 0000 0000b]
      10. 7.6.10 Register 9: CS Configuration Mode Register (address = 09h) [reset = 0000 0000b]
      11. 7.6.11 Register 10: Configuration Register 1 (address = 0Ah) [reset = 0000 0000b]
      12. 7.6.12 Register 11: Configuration Register 2 (address = 0Bh) [reset = 0001 0000b]
      13. 7.6.13 Register 12: Special Functions Register (address = 0Ch) [reset = 0000 0000b]
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Clock Synchronization
      2. 8.1.2 Quiescent Current
      3. 8.1.3 Settling Time
      4. 8.1.4 Overload Recovery
  9. Power Supply Recommendations
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Functional Blocks

Both high-impedance input amplifiers are symmetrical, and have low noise and excellent dc precision. These amplifiers are connected to a resistor network and provide a gain range from 128 V/V down to an attenuation of ⅛. The PGA280 architecture rejects common-mode offsets and noise over a wide bandwidth.

The PGA280 features additional current buffers placed in front of the precision amplifier that can be activated on demand. When activated, these additional current buffers avoid problems that result from input current during dynamic overloads, such as the fast signal transient that follows the channel switching from a multiplexer. Without the use of the additional current buffers, the fast signal transient would overload the precision amplifiers and high bias currents could flow into the protection clamp until the amplifiers recover from the overload. This momentary current can influence the signal source or passive filters in front of the multiplexer and generate long settling tails. Activating this current buffer avoids such an overload current pulse. The buffer disconnects automatically after an adjustable time. For continuous signal measurement, the additional current buffers are not used.

The switches in the input provide signal diagnostic capability and offer an auxiliary input channel (INP2 and INN2; see Figure 44). Both channels can be switched to diagnose or test conditions, such as a ground-referred, single-ended voltage measurement for either input. In this mode, each of the signal inputs can be observed to analyze common-mode offsets and noise.

The primary input channel [INP1 and INN1] provides switches and current sources for a wire break test. Any switch can short both inputs, and can also discharge a filter capacitor after a wire break test, for example.

The signal inputs are diode-clamped to the supply rails. External resistors can be placed in series to the inputs to provide overvoltage protection. Limit current into the input pins to ≤ 10 mA.

The output stage offers a fully-differential signal around the output reference pin, VOCM. The VOCM pin is a high-impedance input and expects an external voltage, typically close to midsupply. The 3-V or 5-V supply of the converter or amplifier, following the PGA280 outputs, is normally connected to VSOP and VSON; this configuration shares a common supply voltage and protects the circuit from overloads. The fully-differential signal avoids coupling of noise and errors from the supply and ground, and allows large signal swing without the risk of nonlinearities that arise when driving near the supply rails.

The PGA280 signal path has several test points for critical overload conditions. The input amplifiers detect signal overvoltage and overload as a result of high gain. The output stage also detects clipping. These events are filtered with adjustable suppression delays and then stored for readout. A GPIO pin can be dedicated for external indication either as an interrupt or in a monitor mode.

A serial peripheral interface (SPI) controls the gain setting and switches, as well as the operation modes and the GPIO port pins. The SPI allows read and write access to the internal registers. These registers contain conditions, flags, and settings, as described in the section. They represent the gain setting for the input stage from 128V/V to the attenuation of ⅛ V/V in binary steps and the output stage gain of 1 V/V and 1.375 V/V (1⅜). The input MUX and switches and the input buffers are also controlled by registers. Internal error conditions are stored and may be masked to activate an external pin in the GPIO port.

This GPIO port can be configured individually for either input or output or for a special function. In special function mode, the port indicates an error condition, generates CS signal, controls an external MUX, and connects to the buffer control and oscillator.

The port pin can act as a CS for an external SPI device. This mode connects other SPI devices [such as an analog-to-digital (A/D) converter] to the primary four-wire SPI. This feature is especially desirable when using galvanically-isolated SPI communication. An optional checksum byte further improves communications integrity.