SBOS487B June 2009 – March 2020 PGA280
CP[6:0]: SPI mode1 or mode2 can be configured for each individual ECS (extended CS) output if activated in Register 9. See CS Mode in for details. CP6 controls ECS6, for example. For SPI mode1, set the respective bit to 1: a positive edge of SCLK follows CS (Clock Polarity, CP = 0). For SPI mode2, set the respective bit to 0: a negative edge of SCLK follows CS (CP = 1). See also Figure 50.