SLLS890C August 2008 – April 2024 TL28L92
PRODUCTION DATA
The Rx FIFO consists of a First-In-First-Out (FIFO) stack with a capacity of 8 or 16 characters. Data is loaded from the receive shift register into the topmost empty position of the FIFO. The RxRDY bit in the status register is set whenever one or more characters are available to be read, and a FFULL status bit is set if all 8 or 16 stack positions are filled with data. Either of these bits can be selected to cause an interrupt. A read of the Rx FIFO outputs the data at the top of the FIFO. After the read cycle, the data FIFO and its associated status bits (see Section 6.3.5) are popped thus emptying a FIFO position for new data.
A disabled receiver with data in its FIFO may generate an interrupt (see Section 6.3.5). Its status bits remain active and its watchdog, if enabled, will continue to operate.