SLLS890C August   2008  – April 2024 TL28L92

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configurations and Functions
  5. 4Electrical Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Static Characteristics for 5V Operation
    3. 4.3 Static Characteristics for 3.3V Operation
    4. 4.4 Dynamic Characteristics for 5V Operation
    5. 4.5 Dynamic Characteristics for 3.3V Operation
    6. 4.6 Typical Performance
    7. 4.7 Timing Diagrams
    8. 4.8 Test Information
  6. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Data Bus Buffer
      2. 5.3.2 Operation Control
      3. 5.3.3 Interrupt Control
      4. 5.3.4 FIFO Configuration
      5. 5.3.5 68xxx Mode
      6. 5.3.6 Timing Circuits
        1. 5.3.6.1  Crystal Clock
        2. 5.3.6.2  Baud Rate Generator
        3. 5.3.6.3  Counter/Timer
        4. 5.3.6.4  Timer Mode
        5. 5.3.6.5  Counter Mode
        6. 5.3.6.6  Time-Out Mode
        7. 5.3.6.7  Time-Out Mode Caution
        8. 5.3.6.8  Communications Channels A and B
        9. 5.3.6.9  Input Port
        10. 5.3.6.10 Output Port
      7. 5.3.7 Operation
        1. 5.3.7.1 Transmitter
        2. 5.3.7.2 Receiver
        3. 5.3.7.3 Transmitter Reset and Disable
        4. 5.3.7.4 Receiver FIFO
        5. 5.3.7.5 Receiver Status Bits
        6. 5.3.7.6 Receiver Reset and Disable
        7. 5.3.7.7 Watchdog
        8. 5.3.7.8 Receiver Time-Out Mode
        9. 5.3.7.9 Time-Out Mode Caution
  7. 6Programming
    1. 6.1 Register Overview
    2. 6.2 Condensed Register Bit Formats
    3. 6.3 Register Descriptions
      1. 6.3.1  Mode Registers
        1. 6.3.1.1 Mode Register 0 Channel A (MR0A)
        2. 6.3.1.2 Mode Register 1 Channel A (MR1A)
        3. 6.3.1.3 Mode Register 2 Channel A (MR2A)
        4. 6.3.1.4 Mode Register 0 Channel B (MR0B)
        5. 6.3.1.5 Mode Register 1 Channel B (MR1B)
        6. 6.3.1.6 Mode Register 2 Channel B (MR2B)
      2. 6.3.2  Clock Select Registers
        1. 6.3.2.1 Clock Select Register Channel A (CSRA)
        2. 6.3.2.2 Clock Select Register Channel B (CSRB)
      3. 6.3.3  Command Registers
        1. 6.3.3.1 Command Register Channel A (CRA)
        2. 6.3.3.2 Command Register Channel B (CRB)
      4. 6.3.4  Status Registers
        1. 6.3.4.1 Status Register Channel A (SRA)
        2. 6.3.4.2 Status Register Channel B (SRB)
      5. 6.3.5  Output Configuration Control Register (OPCR)
      6. 6.3.6  Set Output Port Bits Register (SOPR)
      7. 6.3.7  Reset Output Port Bits Register (ROPR)
      8. 6.3.8  Output Port Register (OPR)
      9. 6.3.9  Auxiliary Control Register (ACR)
      10. 6.3.10 Input Port Change Register (IPCR)
      11. 6.3.11 Interrupt Status Register (ISR)
      12. 6.3.12 Interrupt Mask Register (IMR)
      13. 6.3.13 Interrupt Vector Register (IVR; 68xxx Mode) or General Purpose Register (GP; 80xxx Mode)
      14. 6.3.14 Counter and Timer Registers
    4. 6.4 Output Port Notes
    5. 6.5 CTS, RTS, CTS Enable Tx Signals
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.1.3 Mode Register 2 Channel A (MR2A)

Table 6-26 Mode Register 2 Channel A (MR2A) (Address 0x0) Bit Allocation(1)
76543210
channel modeRTSN Control TxCTSN Enable Txstop bit length
(1) MR2A is accessed when the channel A MR pointer points to MR2, which occurs after any access to MR1A. Accesses to MR2A do not change the pointer.
Table 6-27 Mode Register 2 Channel A (MR2A) (Address 0x0) Bit Description
BIT(S)SYMBOLDESCRIPTION
7 and 6–Channel A mode select. Each channel of the DUART can operate in one of the following four modes:
00 = Normal mode (default)
01 = Automatic echo mode
10 = Local loopback mode
11 = Remote loopback mode
Table 6-28 gives a description of the channel modes.
The user must exercise care when switching into and out of the various modes. The selected mode is activated immediately upon mode selection, even if this occurs in the middle of a received or transmitted character. Likewise, if a mode is deselected the device will switch out of the mode immediately. An exception to this is switching out of auto echo or remote loopback modes: if the deselection occurs just after the receiver has sampled the stop bit (indicated in auto echo by assertion of RxRDY), and the transmitter is enabled, the transmitter will remain in auto echo mode until the entire stop has been retransmitted.
5–Channel A transmitter request to send (RTS) control.
0 = No RTS control
1 = RTS control
This bit controls the deactivation of the RTSAN output (OP0) by the transmitter. This output is normally asserted by setting OPR[0] and negated by resetting OPR[0]. MR2A[5] = 1 caused OPR[0] to be reset automatically one bit time after the characters in the channel A transmit shift register and in the Tx FIFO, if any, are completely transmitted including the programmed number of stop bits, if the transmitter is not enabled.
This feature can be used to automatically terminate the transmission of a message as follows (line turnaround):
  1. Program auto-reset mode: MR2A[5] = 1
  2. Enable transmitter
  3. Assert RTSAN: OPR[0] = 1
  4. Send message
  5. Disable transmitter after the last character is loaded into the channel A Tx FIFO
  6. The last character is transmitted and OPR[0] is reset one bit time after the last stop bit, causing RTSAN to be negated
4–Channel A transmitter clear to send (CTS) control.
0 = Input CTSAN(IP0) has no effect on the transmitter
1 = CTS control enabled
If this bit is a 1, the transmitter checks the state of CTSAN (IP0) each time it is ready to send a character. If IP0 is asserted (LOW), the character is transmitted. If it is negated (HIGH), the TxDA output remains in the marking state and the transmission is delayed until CTSAN goes LOW. Changes in CTSAN while a character is being transmitted do not affect the transmission of that character.
3 to 0–Stop bit length select. This field programs the length of the stop bit appended to the transmitted character. Stop bit lengths of9/16 to 1 and 1 –9/16 to 2 bits, in increments of1/16 bit, can be programmed for character lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1 –1/16 to 2 stop bits can be programmed in increments of1/16 bit. In all cases, the receiver only checks for a mark condition at the center of the stop bit position (one half-bit time after the last data bit, or after the parity bit if enabled is sampled). Refer to Table 6-29 for the values.
If an external 1× clock is used for the transmitter:
MR2A[3] = 0 selects one stop bit
MR2A[3] = 1 selects two stop bits
Table 6-28 DUART Mode Description
MODEDESCRIPTION
NormalThe transmitter and receiver operating independently.
Automatic echoPlaces the channel in the automatic echo mode, which automatically retransmits the received data. The following conditions are true while in automatic echo mode:
  1. Received data is reclocked and retransmitted on the TxDA output
  2. The receive clock is used for the transmitter
  3. The receiver must be enabled, but the transmitter need not be enabled
  4. The channel A TxRDY and TxEMT status bits are inactive
  5. The received parity is checked, but is not regenerated for transmission, i.e. transmitted parity bit is as received
  6. Character framing is checked, but the stop bits are retransmitted as received
  7. A received break is echoed as received until the next valid start bit is detected
  8. CPU to receiver communication continues normally, but the CPU to transmitter link is disabled
Local loopbackSelects local loopback diagnostic mode. In this mode:
  1. The transmitter output is internally connected to the receiver input
  2. The transmit clock is used for the receiver
  3. The TxDA output is held HIGH
  4. The RxDA input is ignored
  5. The transmitter must be enabled, but the receiver need not be enabled
  6. CPU to transmitter and receiver communications continue normally
Remote loopbackSelects remote loopback diagnostic mode. In this mode:
  1. Received data is reclocked and retransmitted on the TxDA output
  2. The receive clock is used for the transmitter
  3. Received data is not sent to the local CPU, and the error status conditions are inactive
  4. The received parity is not checked and is not regenerated for transmission, i.e., transmitted parity is as received
  5. The receiver must be enabled
  6. Character framing is not checked, and the stop bits are retransmitted as received
  7. A received break is echoed as received until the next valid start bit is detected
Table 6-29 Stop Bit Length
MR2A[3:0] (HEXADECIMAL)STOP BIT LENGTH(1)
00.563
10.625
20.688
30.750
40.813
50.875
60.938
71.000
81.563
91.653
A1.688
B1.750
C1.813
D1.875
E1.938
F2.000
(1) Add 0.5 to values shown for 0 to 7 if channel is programmed for 5 bit per character.