SLLS890C August 2008 – April 2024 TL28L92
PRODUCTION DATA
The programming of this register selects which bits in the ISR causes an interrupt output. If a bit in the ISR is a logic 1 and the corresponding bit in the IMR is also a logic 1 the INTRN output is asserted. If the corresponding bit in the IMR is a zero, the state of the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the programmable interrupt outputs OP3 to OP7 or the reading of the ISR.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|
input port change | change break B | RxRDYB FFULLB | TxRDYB | counter ready | change break A | RxRDYA FFULLA | TxRDYA |
BIT(S) | SYMBOL | DESCRIPTION |
---|---|---|
7 | – | Input port change. 0 = not enabled 1 = enabled |
6 | – | Channel B change in break. 0 = not enabled 1 = enabled |
5 | RxRDYB FFULLB | RxB interrupt. 0 = not enabled 1 = enabled |
4 | TxRDYB | TxB interrupt. 0 = not enabled 1 = enabled |
3 | – | Counter ready. 0 = not enabled 1 = enabled |
2 | – | Channel A change in break. 0 = not enabled 1 = enabled |
1 | RxRDYA FFULLA | RxA interrupt. 0 = not enabled 1 = enabled |
0 | TxRDYA | TxA interrupt. 0 = not enabled 1 = enabled |