SLLS890C August 2008 – April 2024 TL28L92
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|
BRG set select | counter/timer mode and clock source select | enable IP3 COS interrupt | enable IP2 COS interrupt | enable IP1 COS interrupt | enable IP0 COS interrupt |
BIT(S) | SYMBOL | DESCRIPTION |
---|---|---|
7 | – | Baud rate generator set select. This bit selects one of two sets of baud rates to be generated by the BRG (see Table 6-32). The selected set of rates is available for use by the channel A and B receivers and transmitters as described in CSRA and CSRB. Baud rate generator characteristics are given in Table 6-33. |
6 to 4 | – | Counter/timer mode and clock source select. This field selects the operating mode of the counter/timer and its clock source as shown in Table 6-51. |
3 to 0 | – | IP3, IP2, IP1 and IP0 change-of-state interrupt enable. 0 = off 1 = enabled This field selects which bits of the input port change register (IPCR) cause the input change bit in the interrupt status register (ISR [7]) to be set. If a bit is in the enabled state the setting of the corresponding bit in the IPCR will also result in the setting of ISR [7], which results in the generation of an interrupt output if IMR [7] = 1. If a bit is in the off state, the setting of that bit in the IPCR has no effect on ISR [7]. |
ACR[6:4] | MODE | CLOCK SOURCE |
---|---|---|
000 | Counter | External IP2 |
001 | Counter | TxCA – 1× clock of channel A transmitter |
010 | Counter | TxCB – 1× clock of channel B transmitter |
011 | Counter | Crystal or external clock (X1/CLK) divided by 16 |
100 | Timer | External (IP2) |
101 | Timer | External (IP2) divided by 16 |
110 | Timer | Crystal or external clock (X1/CLK) |
111 | Timer | Crystal or external clock (X1/CLK) divided by 16 |