In addition to the data word, three status bits (parity error, framing error and received break) are also appended to each data character in the FIFO. The overrun error, MR1[5], is not FIFOed.

Status can be provided in two ways, as programmed by the error mode control bit in the mode register. In the character mode, status is provided on a character-by-character basis; the status applies only to the character at the top of the FIFO. In the block mode, the status provided in the SR for these three bits is the logic OR of the status for all characters coming to the top of the FIFO since the last reset error from the command register was issued. In either mode reading the SR does not affect the FIFO. The FIFO is popped only when the Rx FIFO is read. Therefore the status register should be read prior to reading the FIFO.

If the FIFO is full when a new character is received, that character is held in the receive shift register until a FIFO position is available. If an additional character is received while this state exits, the contents of the FIFO are not affected; the character previously in the shift register is lost and the overrun error status bit (SR[4]) is set upon receipt of the start bit of the new (overrunning) character.

The receiver can control the deactivation of RTS. If programmed to operate in this mode, the RTSN output is negated when a valid start bit was received and the FIFO is full. When a FIFO position becomes available, the RTSN output is reasserted (set LOW) automatically. This feature can be used to prevent an overrun, in the receiver, by connecting the RTSN output to the CTSN input of the transmitting device.

If the receiver is disabled, the FIFO characters can be read. However, no additional characters can be received until the receiver is enabled again. If the receiver is reset, the FIFO and all of the receiver status, and the corresponding output ports and interrupt are reset. No additional characters can be received until the receiver is enabled again.