SLLS890C August   2008  – April 2024 TL28L92

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configurations and Functions
  5. 4Electrical Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Static Characteristics for 5V Operation
    3. 4.3 Static Characteristics for 3.3V Operation
    4. 4.4 Dynamic Characteristics for 5V Operation
    5. 4.5 Dynamic Characteristics for 3.3V Operation
    6. 4.6 Typical Performance
    7. 4.7 Timing Diagrams
    8. 4.8 Test Information
  6. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Data Bus Buffer
      2. 5.3.2 Operation Control
      3. 5.3.3 Interrupt Control
      4. 5.3.4 FIFO Configuration
      5. 5.3.5 68xxx Mode
      6. 5.3.6 Timing Circuits
        1. 5.3.6.1  Crystal Clock
        2. 5.3.6.2  Baud Rate Generator
        3. 5.3.6.3  Counter/Timer
        4. 5.3.6.4  Timer Mode
        5. 5.3.6.5  Counter Mode
        6. 5.3.6.6  Time-Out Mode
        7. 5.3.6.7  Time-Out Mode Caution
        8. 5.3.6.8  Communications Channels A and B
        9. 5.3.6.9  Input Port
        10. 5.3.6.10 Output Port
      7. 5.3.7 Operation
        1. 5.3.7.1 Transmitter
        2. 5.3.7.2 Receiver
        3. 5.3.7.3 Transmitter Reset and Disable
        4. 5.3.7.4 Receiver FIFO
        5. 5.3.7.5 Receiver Status Bits
        6. 5.3.7.6 Receiver Reset and Disable
        7. 5.3.7.7 Watchdog
        8. 5.3.7.8 Receiver Time-Out Mode
        9. 5.3.7.9 Time-Out Mode Caution
  7. 6Programming
    1. 6.1 Register Overview
    2. 6.2 Condensed Register Bit Formats
    3. 6.3 Register Descriptions
      1. 6.3.1  Mode Registers
        1. 6.3.1.1 Mode Register 0 Channel A (MR0A)
        2. 6.3.1.2 Mode Register 1 Channel A (MR1A)
        3. 6.3.1.3 Mode Register 2 Channel A (MR2A)
        4. 6.3.1.4 Mode Register 0 Channel B (MR0B)
        5. 6.3.1.5 Mode Register 1 Channel B (MR1B)
        6. 6.3.1.6 Mode Register 2 Channel B (MR2B)
      2. 6.3.2  Clock Select Registers
        1. 6.3.2.1 Clock Select Register Channel A (CSRA)
        2. 6.3.2.2 Clock Select Register Channel B (CSRB)
      3. 6.3.3  Command Registers
        1. 6.3.3.1 Command Register Channel A (CRA)
        2. 6.3.3.2 Command Register Channel B (CRB)
      4. 6.3.4  Status Registers
        1. 6.3.4.1 Status Register Channel A (SRA)
        2. 6.3.4.2 Status Register Channel B (SRB)
      5. 6.3.5  Output Configuration Control Register (OPCR)
      6. 6.3.6  Set Output Port Bits Register (SOPR)
      7. 6.3.7  Reset Output Port Bits Register (ROPR)
      8. 6.3.8  Output Port Register (OPR)
      9. 6.3.9  Auxiliary Control Register (ACR)
      10. 6.3.10 Input Port Change Register (IPCR)
      11. 6.3.11 Interrupt Status Register (ISR)
      12. 6.3.12 Interrupt Mask Register (IMR)
      13. 6.3.13 Interrupt Vector Register (IVR; 68xxx Mode) or General Purpose Register (GP; 80xxx Mode)
      14. 6.3.14 Counter and Timer Registers
    4. 6.4 Output Port Notes
    5. 6.5 CTS, RTS, CTS Enable Tx Signals
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Register Overview

The operation of the DUART is programmed by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be read by the CPU. The addressing of the registers is described in Table 6-1.

The contents of certain control registers are initialized to zero on RESET. Care should be exercised if the contents of a register are changed during operation, since certain changes may cause operational problems.

For example, changing the number of bits per character while the transmitter is active may cause the transmission of an incorrect character. In general, the contents of the MR, the CSR, and the OPCR should only be changed while the receiver(s) and transmitter(s) are not enabled, and certain changes to the ACR should only be made while the C/T is stopped.

Each channel has three mode registers (MR0, MR1 and MR2) which control the basic configuration of the channel. Access to these registers is controlled by independent MR address pointers. These pointers are set to 0x0 or 0x1 by MR control commands in the command register Miscellaneous Commands. Each time the MR registers are accessed the MR pointer increments, stopping at MR2. It remains pointing to MR2 until set to 0x0 or 0x1 via the miscellaneous commands of the command register. The pointer is set to 0x1 on reset for compatibility with previous TI UART software.

Mode, command, clock select, and status registers are duplicated for each channel to provide total independent operation and control. Refer to Section 6.2 for register bit overview. The reserved registers at addresses 0x2 and 0xA should never be read during normal operation since they are reserved for internal diagnostics.

Table 6-1 TL28L92 Register Addressing READ (RDN = 0), WRITE (WRN = 0)
BINARY ADDRESSREAD OPERATION
(RDN = 0 and CEN = 0)		WRITE OPERATION
(WRN = 0 and CEN = 0)
0000Mode Register A (MR0A, MR1A, MR2A)Mode Register A (MR0A, MR1A, MR2A)
0001Status Register A (SRA)Clock Select Register A (CSRA)
0010ReservedCommand Register A (CRA)
0011Rx Holding Register A (RxFIFOA)Tx Holding Register A (TxFIFOA)
0100Input Port Change Register (IPCR)Auxiliary Control Register (ACR)
0101Interrupt Status Register (ISR)Interrupt Mask Register (IMR)
0110Counter/Timer Upper (CTU)C/T Upper Preset Register (CTPU)
0111Counter/Timer Lower (CTL)C/T Lower Preset Register (CTPL)
1000Mode Register B (MR0B, MR1B, MR2B)Mode Register B (MR0B, MR1B, MR2B)
1001Status Register B (SRB)Clock Select Register B (CSRB)
1010ReservedCommand Register B (CRB)
1011Rx Holding Register B (RxFIFOB)Tx Holding Register B (TxFIFOB)
1100Interrupt vector (68xxx mode)Interrupt vector (68xxx mode)
1100Miscellaneous register (Intel mode), IVR Motorola modeMiscellaneous register (Intel mode), IVR Motorola mode
1101Input Port Register (IPR)Output Port Configuration Register (OPCR)
1110Start counter commandSet Output Port Bits Command (SOPR)
1111Stop counter commandReset Output Port Bits Command (ROPR)
Table 6-2 Registers for Channels A and B
REGISTER NAMECHANNEL A REGISTERCHANNEL B REGISTERACCESS
ModeMRnAMRnBR/W
StatusSRASRBR only
ClockCSRACSRBW only
CommandCRACRBW only
Receiver FIFORxFIFOARxFIFOBR only
Transmitter FIFOTxFIFOATxFIFOBW only
Table 6-3 Registers Supporting Both Channels
REGISTER NAMEMNEMONICACCESS
Input Port ChangeIPCRR
Auxiliary ControlACRW
Interrupt StatusISRR
Interrupt MaskIMRW
Counter/Timer Upper ValueCTUR
Counter/Timer Lower ValueCTLR
Counter/Timer Preset UpperCTPUW
Counter/Timer Preset LowerCTPLW
Input PortIPRR
Output ConfigurationOPCRW
Set Output PortSOPRW
Reset Output PortROPRW
Interrupt Vector or GPIVR/GPR/W