SLLS890C August   2008  – April 2024 TL28L92

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Description
  4. 3Pin Configurations and Functions
  5. 4Electrical Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 Static Characteristics for 5V Operation
    3. 4.3 Static Characteristics for 3.3V Operation
    4. 4.4 Dynamic Characteristics for 5V Operation
    5. 4.5 Dynamic Characteristics for 3.3V Operation
    6. 4.6 Typical Performance
    7. 4.7 Timing Diagrams
    8. 4.8 Test Information
  6. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 Data Bus Buffer
      2. 5.3.2 Operation Control
      3. 5.3.3 Interrupt Control
      4. 5.3.4 FIFO Configuration
      5. 5.3.5 68xxx Mode
      6. 5.3.6 Timing Circuits
        1. 5.3.6.1  Crystal Clock
        2. 5.3.6.2  Baud Rate Generator
        3. 5.3.6.3  Counter/Timer
        4. 5.3.6.4  Timer Mode
        5. 5.3.6.5  Counter Mode
        6. 5.3.6.6  Time-Out Mode
        7. 5.3.6.7  Time-Out Mode Caution
        8. 5.3.6.8  Communications Channels A and B
        9. 5.3.6.9  Input Port
        10. 5.3.6.10 Output Port
      7. 5.3.7 Operation
        1. 5.3.7.1 Transmitter
        2. 5.3.7.2 Receiver
        3. 5.3.7.3 Transmitter Reset and Disable
        4. 5.3.7.4 Receiver FIFO
        5. 5.3.7.5 Receiver Status Bits
        6. 5.3.7.6 Receiver Reset and Disable
        7. 5.3.7.7 Watchdog
        8. 5.3.7.8 Receiver Time-Out Mode
        9. 5.3.7.9 Time-Out Mode Caution
  7. 6Programming
    1. 6.1 Register Overview
    2. 6.2 Condensed Register Bit Formats
    3. 6.3 Register Descriptions
      1. 6.3.1  Mode Registers
        1. 6.3.1.1 Mode Register 0 Channel A (MR0A)
        2. 6.3.1.2 Mode Register 1 Channel A (MR1A)
        3. 6.3.1.3 Mode Register 2 Channel A (MR2A)
        4. 6.3.1.4 Mode Register 0 Channel B (MR0B)
        5. 6.3.1.5 Mode Register 1 Channel B (MR1B)
        6. 6.3.1.6 Mode Register 2 Channel B (MR2B)
      2. 6.3.2  Clock Select Registers
        1. 6.3.2.1 Clock Select Register Channel A (CSRA)
        2. 6.3.2.2 Clock Select Register Channel B (CSRB)
      3. 6.3.3  Command Registers
        1. 6.3.3.1 Command Register Channel A (CRA)
        2. 6.3.3.2 Command Register Channel B (CRB)
      4. 6.3.4  Status Registers
        1. 6.3.4.1 Status Register Channel A (SRA)
        2. 6.3.4.2 Status Register Channel B (SRB)
      5. 6.3.5  Output Configuration Control Register (OPCR)
      6. 6.3.6  Set Output Port Bits Register (SOPR)
      7. 6.3.7  Reset Output Port Bits Register (ROPR)
      8. 6.3.8  Output Port Register (OPR)
      9. 6.3.9  Auxiliary Control Register (ACR)
      10. 6.3.10 Input Port Change Register (IPCR)
      11. 6.3.11 Interrupt Status Register (ISR)
      12. 6.3.12 Interrupt Mask Register (IMR)
      13. 6.3.13 Interrupt Vector Register (IVR; 68xxx Mode) or General Purpose Register (GP; 80xxx Mode)
      14. 6.3.14 Counter and Timer Registers
    4. 6.4 Output Port Notes
    5. 6.5 CTS, RTS, CTS Enable Tx Signals
  8. 7Device and Documentation Support
    1. 7.1 Receiving Notification of Documentation Updates
    2. 7.2 Support Resources
    3. 7.3 Trademarks
    4. 7.4 Electrostatic Discharge Caution
    5. 7.5 Glossary
  9. 8Revision History
  10. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.5 Output Configuration Control Register (OPCR)

This register controls the signal presented by the OP[7:2] pins. The signal presented by the OP[1:0] pins is controlled by the Rx, Tx, and the command register. The default condition of the OP pins is to drive the complement of the data in the OPR[7:0] register.

When OP[7:2] pins drive DMA or interrupt type signals, they switch to open-drain configuration. Otherwise, they drive strong logic 0 or logic 1 levels

Table 6-41 Output Configuration Control Register (OPCR) (Address 0xD) Bit Allocation
76543210
configure OP7configure OP6configure OP5configure OP4configure OP3configure OP2configure OP1configure OP0
Table 6-42 Output Configuration Control Register (OPCR) (Address 0xD) Bit Description
BIT(S)SYMBOLDESCRIPTION
7–OP7 output select
0 = The complement of OPR[7]
1 = The channel B transmitter interrupt output which is the complement of ISR[4]. When in this mode OP7 acts as an open-drain output. Note that this output is not masked by the contents of the IMR.
6–OP6 output select
0 = The complement of OPR[6]
1 = The channel A transmitter interrupt output which is the complement of ISR[0]. When in this mode OP6 acts as an open-drain output. Note that this output is not masked by the contents of the IMR.
5–OP5 output select
0 = The complement of OPR[5]
1 = The channel B receiver interrupt output which is the complement of ISR[5]. When in this mode OP5 acts as an open-drain output. Note that this output is not masked by the contents of the IMR.
4–OP4 output select
0 = The complement of OPR[4]
1 = The channel A receiver interrupt output which is the complement of ISR[1]. When in this mode OP4 acts as an open-drain output. Note that this output is not masked by the contents of the IMR.
3 and 2–OP3 output select
00 = The complement of OPR[3]
01 = The counter/timer output, in which case OP3 acts as an open-drain output. In the timer mode, this output is a square wave at the programmed frequency. In the counter mode, the output remains HIGH until terminal count is reached, at which time it goes LOW. The output returns to the HIGH state when the counter is stopped by a stop counter command. Note that this output is not masked by the contents of the IMR.
10 = The 1× clock for the channel B transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1× clock is output.
11 = The 1× clock for the channel B receiver, which is the clock that samples the received data. If data is not being received, a free running 1× clock is output.
1 and 0–OP2 output select
00 = The complement of OPR[2]
01 = The 16× clock for the channel A transmitter. This is the clock selected by CSRA[3:0], and is a 1× clock if CSRA[3:0] = 1111.
10 = The 1× clock for the channel A transmitter, which is the clock that shifts the transmitted data. If data is not being transmitted, a free running 1× clock is output.
11 = The 1× clock for the channel A receiver, which is the clock that samples the received data. If data is not being received, a free running 1× clock is output.