JAJSER5B February   2018  – February 2025 LMK05028

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
    1. 4.1 Device Start-Up Modes
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Output Clock Test Configurations
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 ITU-T G.8262 (SyncE) Standards Compliance
    2. 7.2 Functional Block Diagrams
      1. 7.2.1 PLL Architecture Overview
      2. 7.2.2 3-Loop Mode
        1. 7.2.2.1 PLL Output Clock Phase Noise Analysis in 3-Loop Mode
      3. 7.2.3 2-Loop REF-DPLL Mode
      4. 7.2.4 2-Loop TCXO-DPLL Mode
      5. 7.2.5 PLL Configurations for Common Applications
    3. 7.3 Feature Description
      1. 7.3.1  Oscillator Input (XO_P/N)
      2. 7.3.2  TCXO/OCXO Input (TCXO_IN)
      3. 7.3.3  Reference Inputs (INx_P/N)
      4. 7.3.4  Clock Input Interfacing and Termination
      5. 7.3.5  Reference Input Mux Selection
        1. 7.3.5.1 Automatic Input Selection
        2. 7.3.5.2 Manual Input Selection
      6. 7.3.6  Hitless Switching
      7. 7.3.7  Gapped Clock Support on Reference Inputs
      8. 7.3.8  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 7.3.8.1 XO Input Monitoring
        2. 7.3.8.2 TCXO Input Monitoring
        3. 7.3.8.3 Reference Input Monitoring
          1. 7.3.8.3.1 Reference Validation Timer
          2. 7.3.8.3.2 Amplitude Monitor
          3. 7.3.8.3.3 Missing Pulse Monitor (Late Detect)
          4. 7.3.8.3.4 Runt Pulse Monitor (Early Detect)
          5. 7.3.8.3.5 Frequency Monitoring
        4. 7.3.8.4 PLL Lock Detectors
        5. 7.3.8.5 Tuning Word History
        6. 7.3.8.6 Status Outputs
        7. 7.3.8.7 Interrupt
      9. 7.3.9  PLL Channels
        1. 7.3.9.1  PLL Frequency Relationships
        2. 7.3.9.2  Analog PLL (APLL)
        3. 7.3.9.3  APLL XO Doubler
        4. 7.3.9.4  APLL Phase Frequency Detector (PFD) and Charge Pump
        5. 7.3.9.5  APLL Loop Filter
        6. 7.3.9.6  APLL Voltage Controlled Oscillator (VCO)
          1. 7.3.9.6.1 VCO Calibration
        7. 7.3.9.7  APLL VCO Post-Dividers (P1, P2)
        8. 7.3.9.8  APLL Fractional N Divider (N) With SDM
        9. 7.3.9.9  REF-DPLL Reference Divider (R)
        10. 7.3.9.10 TCXO/OCXO Input Doubler and M Divider
        11. 7.3.9.11 TCXO Mux
        12. 7.3.9.12 REF-DPLL and TCXO-DPLL Time-to-Digital Converter (TDC)
        13. 7.3.9.13 REF-DPLL and TCXO-DPLL Loop Filter
        14. 7.3.9.14 REF-DPLL and TCXO-DPLL Feedback Dividers
      10. 7.3.10 Output Clock Distribution
      11. 7.3.11 Output Channel Muxes
        1. 7.3.11.1 TCXO/Ref Bypass Mux
      12. 7.3.12 Output Dividers
      13. 7.3.13 Clock Outputs (OUTx_P/N)
        1. 7.3.13.1 AC-Differential Output (AC-DIFF)
        2. 7.3.13.2 HCSL Output
        3. 7.3.13.3 LVCMOS Output (1.8 V, 2.5 V)
        4. 7.3.13.4 Output Auto-Mute During LOL or LOS
      14. 7.3.14 Glitchless Output Clock Start-Up
      15. 7.3.15 Clock Output Interfacing and Termination
      16. 7.3.16 Output Synchronization (SYNC)
      17. 7.3.17 Zero-Delay Mode (ZDM) Configuration
      18. 7.3.18 PLL Cascading With Internal VCO Loopback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Start-Up Modes
        1. 7.4.1.1 EEPROM Mode
        2. 7.4.1.2 ROM Mode
      2. 7.4.2 PLL Operating Modes
        1. 7.4.2.1 Free-Run Mode
        2. 7.4.2.2 Lock Acquisition
        3. 7.4.2.3 Locked Mode
        4. 7.4.2.4 Holdover Mode
      3. 7.4.3 PLL Start-Up Sequence
      4. 7.4.4 Digitally-Controlled Oscillator (DCO) Mode
        1. 7.4.4.1 DCO Frequency Step Size
        2. 7.4.4.2 DCO Direct-Write Mode
      5. 7.4.5 Zero-Delay Mode (ZDM)
      6. 7.4.6 Cascaded PLL Operation
    5. 7.5 Programming
      1. 7.5.1 Interface and Control
      2. 7.5.2 I2C Serial Interface
        1. 7.5.2.1 I2C Block Register Transfers
      3. 7.5.3 SPI Serial Interface
        1. 7.5.3.1 SPI Block Register Transfer
      4. 7.5.4 Register Map Generation
      5. 7.5.5 General Register Programming Sequence
      6. 7.5.6 EEPROM Programming Flow
        1. 7.5.6.1 EEPROM Programming Using Register Commit (Method #1)
          1. 7.5.6.1.1 Write SRAM Using Register Commit
          2. 7.5.6.1.2 Program EEPROM
        2. 7.5.6.2 EEPROM Programming Using Direct SRAM Writes (Method #2)
          1. 7.5.6.2.1 Write SRAM Using Direct Writes
      7. 7.5.7 Read SRAM
      8. 7.5.8 Read EEPROM
      9. 7.5.9 EEPROM Start-Up Mode Default Configuration
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Device Start-Up Sequence
      2. 8.1.2 Power Down (PDN) Pin
      3. 8.1.3 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 8.1.3.1 Mixing Supplies
        2. 8.1.3.2 Power-On Reset (POR) Circuit
        3. 8.1.3.3 Powering Up From a Single-Supply Rail
        4. 8.1.3.4 Power Up From Split-Supply Rails
        5. 8.1.3.5 Non-Monotonic or Slow Power-Up Supply Ramp
      4. 8.1.4 Slow or Delayed XO Start-Up
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 Power Supply Bypassing
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
      3. 8.5.3 Thermal Reliability
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Clock Architect
      2. 9.1.2 TICS Pro
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.4.5 Zero-Delay Mode (ZDM)

Each PLL channel supports the zero-delay mode option to achieve a known and deterministic phase relationship between the reference and output clock. ZDM is supported for 2-loop and 3-loop modes through the REF-DPLL. Once PLL is locked with ZDM enabled, the PLL has minimal phase delay (phase offset) between the reference input and the output clocks. The input-to-output phase offset (tPHO) is repeatable after exiting holdover, after a switchover event, and after device start-up. Note that ZDM and DCO mode must not be enabled at the same time within a PLL channel.

As shown in Figure 7-42, PLL1 supports zero-delay for OUT4/5, OUT6, and OUT7. PLL2 supports zero-delay for OUT0, OUT1, and OUT2/3 through as similar ZDM configuration. See Zero-Delay Mode (ZDM) Configuration.

LMK05028 DPLL1 ZDM Configuration for OUT4 to OUT7Figure 7-42 DPLL1 ZDM Configuration for OUT4 to OUT7