SBASAE4 December   2025 ADS125P08

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 SFDR Measurement
    12. 6.12 Noise Performance
    13. 6.13 TUE (Total Unadjusted Error) Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Multiplexer
      2. 7.3.2  High-Impedance Input Buffers
      3. 7.3.3  Input Range
      4. 7.3.4  ADC Reference Voltage
      5. 7.3.5  Power Supplies
        1. 7.3.5.1 AVDD and AVSS
        2. 7.3.5.2 IOVDD
        3. 7.3.5.3 CAPA and CAPD
        4. 7.3.5.4 Power-On Reset (POR)
      6. 7.3.6  Clock Operation
        1. 7.3.6.1 Internal Oscillator
        2. 7.3.6.2 External Clock
      7. 7.3.7  Modulator
      8. 7.3.8  Digital Filter
        1. 7.3.8.1 Digital Filter Latency
        2. 7.3.8.2 Sinc3 and Sinc4 Filters
        3. 7.3.8.3 Sinc4 + Sinc1 Cascade Filter
        4. 7.3.8.4 50/60Hz Notch Filters
      9. 7.3.9  FIFO Buffer
        1. 7.3.9.1 FIFO Buffer Read and Write
        2. 7.3.9.2 FIFO Overflow and Underflow
        3. 7.3.9.3 FIFO Depth Indicator
        4. 7.3.9.4 FIFO Enable and Flush
        5. 7.3.9.5 FIFO Thresholds
      10. 7.3.10 Channel Auto-Sequencer
        1. 7.3.10.1 Auto-Sequencer: Basic Operation
        2. 7.3.10.2 Sequencer Modes
          1. 7.3.10.2.1 Single-Shot Mode
          2. 7.3.10.2.2 Single Step Continuous Conversion Mode
          3. 7.3.10.2.3 Single Sequence Mode
          4. 7.3.10.2.4 Continuous Sequence Mode
        3. 7.3.10.3 Configuring the Auto-Sequencer
        4. 7.3.10.4 Starting and Stopping the Sequencer
        5. 7.3.10.5 Auto-Sequencer and DRDY Behavior
      11. 7.3.11 Offset and Gain Calibration
      12. 7.3.12 General Purpose IOs (GPIOs)
        1. 7.3.12.1 DRDY Output
        2. 7.3.12.2 FAULT Output
      13. 7.3.13 Burn-Out Current Sources
      14. 7.3.14 Open Wire Detection with ADC 0-code output
      15. 7.3.15 System Monitors
        1. 7.3.15.1 Internal Short (Offset Calibration)
        2. 7.3.15.2 Internal Temperature Sensor
        3. 7.3.15.3 External Reference Voltage Readback
        4. 7.3.15.4 Power-Supply Readback
      16. 7.3.16 Monitor Flags, Indicators and Counters
        1. 7.3.16.1  Reset (RESETn flag)
        2. 7.3.16.2  AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.16.3  Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.16.4  Modulator Overrange Monitor (MOD_OVR_FAULTn flag)
        5. 7.3.16.5  Register Map CRC (REG_MAP_CRC_FAULTn flag)
        6. 7.3.16.6  Memory Map CRC (MEM_INTERNAL_FAULTn flag)
        7. 7.3.16.7  FIFO Overflow (FIFO_OFn flag) and FIFO Underflow (FIFO_UFn flag)
        8. 7.3.16.8  FIFO CRC Fault (FIFO_CRC_FAULTn flag)
        9. 7.3.16.9  GPIO Readback
        10. 7.3.16.10 SPI CRC Fault (SPI_CRC_FAULTn flag)
        11. 7.3.16.11 Register Write Fault (REG_WRITE_FAULTn flag)
        12. 7.3.16.12 DRDY Indicator (DRDY bit)
        13. 7.3.16.13 Sequencer Active Indicator (SEQ_ACTIVE bit)
        14. 7.3.16.14 Sequence Step Indicator (STEP_INDICATOR[4:0])
        15. 7.3.16.15 ADC Conversion Counter (CONV_COUNT[3:0])
        16. 7.3.16.16 FIFO Depth Indicator (FIFO_DEPTH[8:0])
        17. 7.3.16.17 Completed Sequence Counter (SEQ_COUNT[3:0])
      17. 7.3.17 Test DAC (TDAC)
      18. 7.3.18 Parallel Post Filters
        1. 7.3.18.1 Configuring the Parallel Post Filters
        2. 7.3.18.2 Frequency Response of the Parallel Post Filters
        3. 7.3.18.3 Settling Times and DRDY Behavior When Using the Post Filters
        4. 7.3.18.4 Examples of Recommended Post Filter Settings
      19. 7.3.19 Chip Select Forwarding
        1. 7.3.19.1 Configuring the CS forward feature
        2. 7.3.19.2 CS Forward Timeout
        3. 7.3.19.3 CS Forward Header, Frame, and State Diagram
        4. 7.3.19.4 Disabling the CS-FWD mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Scalable Speed Modes
      2. 7.4.2 Sequencer Functional Modes
      3. 7.4.3 Idle Mode and Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
      7. 7.4.7 Conversion-Start Delay Time
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No-Operation
        2. 7.5.4.2 Read Conversion Data
        3. 7.5.4.3 Read Register Command
        4. 7.5.4.4 Write Register Command
        5. 7.5.4.5 Read FIFO Buffer Command
      5. 7.5.5  Continuous Read Mode
        1. 7.5.5.1 Read Conversion Data in Continuous Read Mode
        2. 7.5.5.2 Read Registers in Continuous Read Mode
        3. 7.5.5.3 Read FIFO Buffer in Continuous Read Mode
      6. 7.5.6  SPI communication after POR or Reset
      7. 7.5.7  DRDY Pin Behavior
      8. 7.5.8  Daisy-Chain Operation
      9. 7.5.9  3-Wire SPI Mode
        1. 7.5.9.1 3-Wire SPI Mode Frame Re-Align
      10. 7.5.10 Conversion Data
      11. 7.5.11 Data Ready
        1. 7.5.11.1 DRDY Pin and SDO/DRDY Pin
        2. 7.5.11.2 DRDY Bit
        3. 7.5.11.3 Clock Counting
    6. 7.6 Register Map
      1. 7.6.1 ADS125P08 Status and General Configuration Page
      2. 7.6.2 ADS125P08 Step Configuration Page
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Serial Interface Connections
      2. 8.1.2 Interfacing with Multiple Devices
      3. 8.1.3 Unused Inputs and Outputs
      4. 8.1.4 Device Initialization
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plots - Crosstalk
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supplies
      2. 8.3.2 Power-Supply Sequencing
      3. 8.3.3 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.19.3 CS Forward Header, Frame, and State Diagram

After the CS-FWD mode is enabled, the UDP communication is started by sending the CS Forward Header frame as shown in Table 7-42. The first byte on SDI includes the CS forward index or SPI index as 4 MSBs. This is the destination device selection, 0h00 to 0h0B where 0h00 is destination device 1, 0h01 is destination device 2 and so on. The first byte on SDI also includes the number of frames to be transferred as 4LSBs. The second byte on SDI includes the CRC for the preceding data, if CRC is enabled. The third byte (do not care) is always required: When in CS-FWD mode, three bytes per frame are always required for the header frame to communicate with the CS-FWD controller.

Table 7-42 CS Forward Header Frame
SIGNAL 1stBYTE 2ndBYTE 3rdBYTE
SDI

SPI index (4 MSBs)

and

frame# bits (4 LSBs)

CRC (if CRC enabled)

 Don’t care
SDO

FFh

 1stbyte received on SDI

CRC check result (if CRC enabled)

The SPI index (4 MSBs) of the first byte in the header indicates which destination device is selected, Table 7-43 describes the exact mapping of these bits to a specific destination device.

Table 7-43 SPI Index Selection
SPI INDEX DESTINATION DEVICE SELECTED
0000b The device, ADS125P08
0001b Destination device 1, connected to GPIO0
0010b Destination device 2, connected to GPIO1
0011b Destination device 3, connected to GPIO2
0100b Destination device 4, connected to GPIO3
0101b Destination device 5, connected to AGPIO0
0110b Destination device 6, connected to AGPIO1
0111b Destination device 7, connected to AGPIO2
1000b Destination device 8, connected to AGPIO3
1001b Destination device 9, connected to AGPIO4
1010b Destination device 10, connected to AGPIO5
1011b Destination device 11, connected to AGPIO6
1100b Destination device 12, connected to AGPIO7
all other codes Reserved

The frame number bits (4LSBs) of the first byte in the header in Table 7-42 sent from the host indicate the number of frames sent to the selected destination device as shown in Table 7-44. After the specified number of frames are sent to the selected destination device, the CS-FWD controller expects another header frame with new information regarding the next destination device selection and number of frames to be sent. The CS-FWD controller stays in CS-FWD mode until the user explicitly chooses to exit this mode, see the Disabling the CS-FWD mode section for details on exiting the mode.

Table 7-44 CS-FWD Frame Number Indication
FRAME NUMBER LSBS NUMBER OF CS-FWD FRAMES SENT
0000b 1
0001b 2
0010b 3
0011b 4
... ...
1110b 15
1111b 16

During an UDP sequence, a header response frame is sent from the device on SDO as shown in Table 7-42, this response is denoted as Ack in the following, as shown in Figure 7-37. This consists of bits[23:16] = FFh to represent the device writing to the host, bits[15:8] repeat the data sent to initiate the UDP (first byte on SDI), and Bits[7:0] are a correct CRC for the preceding data using the polynomial x8 +x2 + x + 1. This byte of CRC is required only when CRC is enabled for the SPI, otherwise the byte is 0hFF.

The host can distinguish whether the host is communicating with the CS forward controller or any other destination device based on the SDO received. If talking to the controller, the host receives the SDO as FFh and the mirrored bytes received by the controller. So the host can check if the bytes received by the controller are correct or not and then decide how to respond: keep timeout and re-send the commands to the controller if the bytes are incorrect.

Figure 7-37 shows a timing diagram for a typical CS-FWD communication sequence. In the first header frame shown, the SPI index is set to target device M. Therefore, in the subsequent frames, the CS signal is only forwarded to device M (j is the number of frames for communication to device M as specified in the header frame). In the 2nd header frame, device N is specified and communication to device N is performed in subsequent frames (k is the number of frames for communication to device N).

Figure 7-37 also indicates the responses sent from the target device to SDO. Simultaneously with each header frame, the Ack frame of the target device is visible on SDO. Thereafter, the target device sends command or data bytes to SDO depending on the commands used, for simplicity those are indicated by Ack(M) for device M and Ack(N) for device N in Figure 7-37.

The condition for a qualified forward frame is to have a minimum of at least 8 SCLK cycles when CSn is low. However, the frames can be longer than 8 SCLK cycles, and subsequent frames can differ in length. There is no maximum limit on the frame length.

ADS125P08 CS Forward Timing Diagram Figure 7-37 CS Forward Timing Diagram

The following error handling is recommended to provide robustness of the communication with and without CRC enabled:

  • CRC is enabled: If the host detects a CRC error when receiving data from a device, the host must repeat the command to the controller until the correct CRC is received by the host. Similarly, if the CRC error is detected by the SPI controller device in the header, the controller must keep receiving the header from the host until the CRC check is correct.
  • CRC is disabled: If the 2nd byte on SDO does not match the 1st byte sent to the device, the host must cause the timeout without toggling SCLK in the immediate next frame.

Figure 7-38 depicts the state diagram for the CS-FWD controller. As soon as the CS forward is enabled, the controller is expecting to receive a valid header frame. Once a valid header frame is received, the communication with the selected destination device is started, and continues until the pre-defined number of frames are completed, or a timeout occurs, or the CS forward mode is disabled in the SPI controller device.

ADS125P08 CS Forward State Diagram Figure 7-38 CS Forward State Diagram