SBASAE4 December   2025 ADS125P08

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 SFDR Measurement
    12. 6.12 Noise Performance
    13. 6.13 TUE (Total Unadjusted Error) Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Multiplexer
      2. 7.3.2  High-Impedance Input Buffers
      3. 7.3.3  Input Range
      4. 7.3.4  ADC Reference Voltage
      5. 7.3.5  Power Supplies
        1. 7.3.5.1 AVDD and AVSS
        2. 7.3.5.2 IOVDD
        3. 7.3.5.3 CAPA and CAPD
        4. 7.3.5.4 Power-On Reset (POR)
      6. 7.3.6  Clock Operation
        1. 7.3.6.1 Internal Oscillator
        2. 7.3.6.2 External Clock
      7. 7.3.7  Modulator
      8. 7.3.8  Digital Filter
        1. 7.3.8.1 Digital Filter Latency
        2. 7.3.8.2 Sinc3 and Sinc4 Filters
        3. 7.3.8.3 Sinc4 + Sinc1 Cascade Filter
        4. 7.3.8.4 50/60Hz Notch Filters
      9. 7.3.9  FIFO Buffer
        1. 7.3.9.1 FIFO Buffer Read and Write
        2. 7.3.9.2 FIFO Overflow and Underflow
        3. 7.3.9.3 FIFO Depth Indicator
        4. 7.3.9.4 FIFO Enable and Flush
        5. 7.3.9.5 FIFO Thresholds
      10. 7.3.10 Channel Auto-Sequencer
        1. 7.3.10.1 Auto-Sequencer: Basic Operation
        2. 7.3.10.2 Sequencer Modes
          1. 7.3.10.2.1 Single-Shot Mode
          2. 7.3.10.2.2 Single Step Continuous Conversion Mode
          3. 7.3.10.2.3 Single Sequence Mode
          4. 7.3.10.2.4 Continuous Sequence Mode
        3. 7.3.10.3 Configuring the Auto-Sequencer
        4. 7.3.10.4 Starting and Stopping the Sequencer
        5. 7.3.10.5 Auto-Sequencer and DRDY Behavior
      11. 7.3.11 Offset and Gain Calibration
      12. 7.3.12 General Purpose IOs (GPIOs)
        1. 7.3.12.1 DRDY Output
        2. 7.3.12.2 FAULT Output
      13. 7.3.13 Burn-Out Current Sources
      14. 7.3.14 Open Wire Detection with ADC 0-code output
      15. 7.3.15 System Monitors
        1. 7.3.15.1 Internal Short (Offset Calibration)
        2. 7.3.15.2 Internal Temperature Sensor
        3. 7.3.15.3 External Reference Voltage Readback
        4. 7.3.15.4 Power-Supply Readback
      16. 7.3.16 Monitor Flags, Indicators and Counters
        1. 7.3.16.1  Reset (RESETn flag)
        2. 7.3.16.2  AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.16.3  Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.16.4  Modulator Overrange Monitor (MOD_OVR_FAULTn flag)
        5. 7.3.16.5  Register Map CRC (REG_MAP_CRC_FAULTn flag)
        6. 7.3.16.6  Memory Map CRC (MEM_INTERNAL_FAULTn flag)
        7. 7.3.16.7  FIFO Overflow (FIFO_OFn flag) and FIFO Underflow (FIFO_UFn flag)
        8. 7.3.16.8  FIFO CRC Fault (FIFO_CRC_FAULTn flag)
        9. 7.3.16.9  GPIO Readback
        10. 7.3.16.10 SPI CRC Fault (SPI_CRC_FAULTn flag)
        11. 7.3.16.11 Register Write Fault (REG_WRITE_FAULTn flag)
        12. 7.3.16.12 DRDY Indicator (DRDY bit)
        13. 7.3.16.13 Sequencer Active Indicator (SEQ_ACTIVE bit)
        14. 7.3.16.14 Sequence Step Indicator (STEP_INDICATOR[4:0])
        15. 7.3.16.15 ADC Conversion Counter (CONV_COUNT[3:0])
        16. 7.3.16.16 FIFO Depth Indicator (FIFO_DEPTH[8:0])
        17. 7.3.16.17 Completed Sequence Counter (SEQ_COUNT[3:0])
      17. 7.3.17 Test DAC (TDAC)
      18. 7.3.18 Parallel Post Filters
        1. 7.3.18.1 Configuring the Parallel Post Filters
        2. 7.3.18.2 Frequency Response of the Parallel Post Filters
        3. 7.3.18.3 Settling Times and DRDY Behavior When Using the Post Filters
        4. 7.3.18.4 Examples of Recommended Post Filter Settings
      19. 7.3.19 Chip Select Forwarding
        1. 7.3.19.1 Configuring the CS forward feature
        2. 7.3.19.2 CS Forward Timeout
        3. 7.3.19.3 CS Forward Header, Frame, and State Diagram
        4. 7.3.19.4 Disabling the CS-FWD mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Scalable Speed Modes
      2. 7.4.2 Sequencer Functional Modes
      3. 7.4.3 Idle Mode and Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
      7. 7.4.7 Conversion-Start Delay Time
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No-Operation
        2. 7.5.4.2 Read Conversion Data
        3. 7.5.4.3 Read Register Command
        4. 7.5.4.4 Write Register Command
        5. 7.5.4.5 Read FIFO Buffer Command
      5. 7.5.5  Continuous Read Mode
        1. 7.5.5.1 Read Conversion Data in Continuous Read Mode
        2. 7.5.5.2 Read Registers in Continuous Read Mode
        3. 7.5.5.3 Read FIFO Buffer in Continuous Read Mode
      6. 7.5.6  SPI communication after POR or Reset
      7. 7.5.7  DRDY Pin Behavior
      8. 7.5.8  Daisy-Chain Operation
      9. 7.5.9  3-Wire SPI Mode
        1. 7.5.9.1 3-Wire SPI Mode Frame Re-Align
      10. 7.5.10 Conversion Data
      11. 7.5.11 Data Ready
        1. 7.5.11.1 DRDY Pin and SDO/DRDY Pin
        2. 7.5.11.2 DRDY Bit
        3. 7.5.11.3 Clock Counting
    6. 7.6 Register Map
      1. 7.6.1 ADS125P08 Status and General Configuration Page
      2. 7.6.2 ADS125P08 Step Configuration Page
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Serial Interface Connections
      2. 8.1.2 Interfacing with Multiple Devices
      3. 8.1.3 Unused Inputs and Outputs
      4. 8.1.4 Device Initialization
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plots - Crosstalk
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supplies
      2. 8.3.2 Power-Supply Sequencing
      3. 8.3.3 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.8.3 Sinc4 + Sinc1 Cascade Filter

For selected data rates, the sinc4 filter offers the option of a cascade sinc1 filter section. Compared to a single-stage sinc3 or sinc4 filter, cascading the sinc1 filter shortens latency time when operated at the same data rate. However, the sinc3 and sinc4 filters provide greater rejection of interference signals close to the notch frequencies because of the wide frequency-rejection range at the data rate frequency. When operated in cascade mode, the OSR of the sinc4 stage is fixed at 32 (OSR = A) and the decimation of the sinc1 stage (OSR = B) determines the output data rate. The first stage of the cascade filter is fixed to sinc4, meaning the sinc filter configuration set by the STEPx_FLTR_MODE bit in the STEPx_FLTR1_CFG registers is ignored (where x = 0 to 31 for the sequence step). Table 7-12 summarizes the cascade filter characteristics.

Table 7-12 Sinc4 + Sinc1 Cascade Filter Characteristics
SPEED

MODE

 fCLK
(MHz)		 OSR (A × B)(1) DATA RATE
(SPS)		 –3dB FREQUENCY (Hz) LATENCY TIME (μs)
3 25.6 64 (32 × 2) 200000 88320 13.60
2 12.8 100000 44160 27.10
1 3.2 25000 11040 108.40
0 1.6 12500 5520 216.90
3 25.6 128 (32 × 4) 100000 44160 18.60
2 12.8 50000 22080 37.10
1 3.2 12500 5520 148.40
0 1.6 6250 2760 296.90
3 25.6 256 (32 × 8) 50000 22080 28.60
2 12.8 25000 11040 57.10
1 3.2 6250 2760 228.40
0 1.6 3125 1380 456.90
3 25.6 512 (32 × 16) 25000 11040 48.60
2 12.8 12500 5520 97.10
1 3.2 3125 1380 388.40
0 1.6 1562.5 690 776.90
3 25.6 1024 (32 × 32) 12500 5520 88.60
2 12.8 6250 2760 177.10
1 3.2 1562.5 690 708.40
0 1.6 781.25 345 1416.90
3 25.6 2048 (32 × 64) 6250 2760 168.60
2 12.8 3125 1380 337.10
1 3.2 781.25 345 1348.40
0 1.6 390.63 172.5 2696.90
3 25.6 4000 (32 × 125) 3200 1413.12 321.10
2 12.8 1600 706.56 642.10
1 3.2 400 176.64 2568.40
0 1.6 200 88.32 5136.90
3 25.6 8000 (32 × 250) 1600 706.56 633.60
2 12.8 800 353.28 1267.10
1 3.2 200 88.32 5068.40
0 1.6 100 44.16 10136.90
3 25.6 16000 (32 × 500) 800 353.28 1258.60
2 12.8 400 176.64 2517.10
1 3.2 100 44.16 10068.40
0 1.6 50 22.08 20136.90
3 25.6 26656 (32 × 833) 480.19 212.052 2091.10
2 12.8 240.1 106.028 4182.10
1 3.2 60.02 26.505 16728.40
0 1.6 30.01 13.252 33456.90
3 25.6 32000 (32 × 1000) 400 176.64 2508.60
2 12.8 200 88.32 5017.10
1 3.2 50 22.08 20068.40
0 1.6 25 11.04 40136.90
3 25.6 96000 (32 × 3000) 133.33 58.879 7508.60
2 12.8 66.67 29.441 15017.10
1 3.2 16.67 7.361 60068.40
0 1.6 8.33 3.679 120136.90
3 25.6 160000 (32 × 5000) 80 35.328 12508.60
2 12.8 40 17.664 25017.10
1 3.2 10 4.416 100068.40
0 1.6 5 2.208 200136.90
(1) A = OSR of the sinc4 first stage, B = OSR of the sinc1 second stage.

Figure 7-14 illustrates the frequency response of the sinc4 + sinc1 cascade filter for OSR = 26667 and 32000, representing fDATA = 50 SPS and 60 SPS in speed mode 1 operation. Nulls in the frequency response occur at n × fDATA, n = 1, 2, 3, and so on. At the null frequencies, the filter has zero gain. Assuming no ADC clock frequency error, the normal-mode rejection is 34dB (typical) over a ±2% signal frequency variation at the null frequencies.

ADS125P08 Sinc4 + Sinc1 Cascaded Filter Frequency Response Figure 7-14 Sinc4 + Sinc1 Cascaded Filter Frequency Response

Table 7-14 summarizes the 50Hz and 60Hz line-cycle rejection based on 2% (1Hz in 50Hz case) and 6% ratio tolerance of power-line to ADC clock frequency.

Table 7-13 50Hz and 60Hz Line Cycle Rejection for Cascade Filter
SPEED

MODE

(1)		 OSR Filter type fDATA (SPS) DIGITAL FILTER RESPONSE (dB)
50Hz ±1Hz 60Hz ±1Hz
CLOCK TOLERANCE: (2)
0% 1% 0% 1%
0 160000

(32 × 5000)

 Sinc4 5 -34.4 -31.5 -36.0 -32.8
1 160000

(32 × 5000)

 Sinc4 10 -33.9 -30.5 -35.6 -31.6
1 96000

(32 × 3000)

 Sinc4 16.6 -33.9 -30.3 -21.0 -20.8
0 32000

(32 × 1000)

 Sinc4 25 -33.8 -30.2 -17.8 -17.8
1 32000

(32 × 1000)

 Sinc4 50 -33.8 -30.2 -15.6 -15.3
1 26656

(32 × 833)

 Sinc4 60 -15.0 -14.7 -35.2 -31.2
0 16000

(32 × 500)

 Sinc4 50 -33.8 -30.2 -15.6 -15.3
(1) Nominal clock frequency for each speed mode is used: fCLK = 25.6MHz (speed mode 3), 12.8MHz (speed mode 2), 3.2MHz (speed mode 1), 1.6MHz (speed mode 0).
(2) 0% clock tolerance corresponds to external clock, 1% clock tolerance corresponds to internal clock.