SBASAE4 December   2025 ADS125P08

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 SFDR Measurement
    12. 6.12 Noise Performance
    13. 6.13 TUE (Total Unadjusted Error) Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Multiplexer
      2. 7.3.2  High-Impedance Input Buffers
      3. 7.3.3  Input Range
      4. 7.3.4  ADC Reference Voltage
      5. 7.3.5  Power Supplies
        1. 7.3.5.1 AVDD and AVSS
        2. 7.3.5.2 IOVDD
        3. 7.3.5.3 CAPA and CAPD
        4. 7.3.5.4 Power-On Reset (POR)
      6. 7.3.6  Clock Operation
        1. 7.3.6.1 Internal Oscillator
        2. 7.3.6.2 External Clock
      7. 7.3.7  Modulator
      8. 7.3.8  Digital Filter
        1. 7.3.8.1 Digital Filter Latency
        2. 7.3.8.2 Sinc3 and Sinc4 Filters
        3. 7.3.8.3 Sinc4 + Sinc1 Cascade Filter
        4. 7.3.8.4 50/60Hz Notch Filters
      9. 7.3.9  FIFO Buffer
        1. 7.3.9.1 FIFO Buffer Read and Write
        2. 7.3.9.2 FIFO Overflow and Underflow
        3. 7.3.9.3 FIFO Depth Indicator
        4. 7.3.9.4 FIFO Enable and Flush
        5. 7.3.9.5 FIFO Thresholds
      10. 7.3.10 Channel Auto-Sequencer
        1. 7.3.10.1 Auto-Sequencer: Basic Operation
        2. 7.3.10.2 Sequencer Modes
          1. 7.3.10.2.1 Single-Shot Mode
          2. 7.3.10.2.2 Single Step Continuous Conversion Mode
          3. 7.3.10.2.3 Single Sequence Mode
          4. 7.3.10.2.4 Continuous Sequence Mode
        3. 7.3.10.3 Configuring the Auto-Sequencer
        4. 7.3.10.4 Starting and Stopping the Sequencer
        5. 7.3.10.5 Auto-Sequencer and DRDY Behavior
      11. 7.3.11 Offset and Gain Calibration
      12. 7.3.12 General Purpose IOs (GPIOs)
        1. 7.3.12.1 DRDY Output
        2. 7.3.12.2 FAULT Output
      13. 7.3.13 Burn-Out Current Sources
      14. 7.3.14 Open Wire Detection with ADC 0-code output
      15. 7.3.15 System Monitors
        1. 7.3.15.1 Internal Short (Offset Calibration)
        2. 7.3.15.2 Internal Temperature Sensor
        3. 7.3.15.3 External Reference Voltage Readback
        4. 7.3.15.4 Power-Supply Readback
      16. 7.3.16 Monitor Flags, Indicators and Counters
        1. 7.3.16.1  Reset (RESETn flag)
        2. 7.3.16.2  AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.16.3  Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.16.4  Modulator Overrange Monitor (MOD_OVR_FAULTn flag)
        5. 7.3.16.5  Register Map CRC (REG_MAP_CRC_FAULTn flag)
        6. 7.3.16.6  Memory Map CRC (MEM_INTERNAL_FAULTn flag)
        7. 7.3.16.7  FIFO Overflow (FIFO_OFn flag) and FIFO Underflow (FIFO_UFn flag)
        8. 7.3.16.8  FIFO CRC Fault (FIFO_CRC_FAULTn flag)
        9. 7.3.16.9  GPIO Readback
        10. 7.3.16.10 SPI CRC Fault (SPI_CRC_FAULTn flag)
        11. 7.3.16.11 Register Write Fault (REG_WRITE_FAULTn flag)
        12. 7.3.16.12 DRDY Indicator (DRDY bit)
        13. 7.3.16.13 Sequencer Active Indicator (SEQ_ACTIVE bit)
        14. 7.3.16.14 Sequence Step Indicator (STEP_INDICATOR[4:0])
        15. 7.3.16.15 ADC Conversion Counter (CONV_COUNT[3:0])
        16. 7.3.16.16 FIFO Depth Indicator (FIFO_DEPTH[8:0])
        17. 7.3.16.17 Completed Sequence Counter (SEQ_COUNT[3:0])
      17. 7.3.17 Test DAC (TDAC)
      18. 7.3.18 Parallel Post Filters
        1. 7.3.18.1 Configuring the Parallel Post Filters
        2. 7.3.18.2 Frequency Response of the Parallel Post Filters
        3. 7.3.18.3 Settling Times and DRDY Behavior When Using the Post Filters
        4. 7.3.18.4 Examples of Recommended Post Filter Settings
      19. 7.3.19 Chip Select Forwarding
        1. 7.3.19.1 Configuring the CS forward feature
        2. 7.3.19.2 CS Forward Timeout
        3. 7.3.19.3 CS Forward Header, Frame, and State Diagram
        4. 7.3.19.4 Disabling the CS-FWD mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Scalable Speed Modes
      2. 7.4.2 Sequencer Functional Modes
      3. 7.4.3 Idle Mode and Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
      7. 7.4.7 Conversion-Start Delay Time
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No-Operation
        2. 7.5.4.2 Read Conversion Data
        3. 7.5.4.3 Read Register Command
        4. 7.5.4.4 Write Register Command
        5. 7.5.4.5 Read FIFO Buffer Command
      5. 7.5.5  Continuous Read Mode
        1. 7.5.5.1 Read Conversion Data in Continuous Read Mode
        2. 7.5.5.2 Read Registers in Continuous Read Mode
        3. 7.5.5.3 Read FIFO Buffer in Continuous Read Mode
      6. 7.5.6  SPI communication after POR or Reset
      7. 7.5.7  DRDY Pin Behavior
      8. 7.5.8  Daisy-Chain Operation
      9. 7.5.9  3-Wire SPI Mode
        1. 7.5.9.1 3-Wire SPI Mode Frame Re-Align
      10. 7.5.10 Conversion Data
      11. 7.5.11 Data Ready
        1. 7.5.11.1 DRDY Pin and SDO/DRDY Pin
        2. 7.5.11.2 DRDY Bit
        3. 7.5.11.3 Clock Counting
    6. 7.6 Register Map
      1. 7.6.1 ADS125P08 Status and General Configuration Page
      2. 7.6.2 ADS125P08 Step Configuration Page
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Serial Interface Connections
      2. 8.1.2 Interfacing with Multiple Devices
      3. 8.1.3 Unused Inputs and Outputs
      4. 8.1.4 Device Initialization
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plots - Crosstalk
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supplies
      2. 8.3.2 Power-Supply Sequencing
      3. 8.3.3 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD - AVSS =  5 V, IOVDD = 1.8 V, VIN = 0 V, VCM = (AVDD - AVSS)/2, (VREFP – VREFN) =  2.5 V, all speed modes, input buffers on, external clock, and reference buffer on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS, SPEED MODE 3
Input current,
differential input voltage		 VCM=AVDD/2 Input buffers off ±3 µA
Input buffers on ±7 nA
Input current drift,
differential input voltage		 VCM=AVDD/2 Input buffers off 5 nA/°C
Input buffers on 0.07 nA/°C
Input current,
common-mode input voltage		 VN=VP Input buffers off ±3 µA
Input buffers on ±7 nA
ANALOG INPUTS, SPEED MODE 2
Input current,
differential input voltage		 VCM=AVDD/2 Input buffers off ±1.5 µA
Input buffers on ±2 nA
Input current drift,
differential input voltage		 VCM=AVDD/2 Input buffers off 5 nA/°C
Input buffers on 0.02 nA/°C
Input current,
common-mode input voltage		 VN=VP Input buffers off ±1.5 µA
Input buffers on ±3 nA
ANALOG INPUTS, SPEED MODE 1
Input current,
differential input voltage		 VCM=AVDD/2 Input buffers off ±0.4 µA
Input buffers on ±2 nA
Input current drift,
differential input voltage		 VCM=AVDD/2 Input buffers off 5 nA/°C
Input buffers on 0.02 nA/°C
Input current,
common-mode input voltage		 VN=VP Input buffers off ±0.4 µA
Input buffers on ±2 nA
ANALOG INPUTS, SPEED MODE 0
Input current,
differential input voltage		 VCM=AVDD/2 Input buffers off ±0.4 µA
Input buffers on ±1 nA
Input current drift,
differential input voltage		 VCM=AVDD/2 Input buffers off 0.2 nA/°C
Input buffers on 0.01 nA/°C
Input current,
common-mode input voltage		 VN=VP Input buffers off ±0.4 µA
Input buffers on ±1 nA
DC PERFORMANCE
Resolution OSR ≥ 32 24 Bits
Noise See the Noise Performance section for details
INL Integral nonlinearity TA = -40°C to 125°C Speed mode 3, buffer on 2 7 ppm of FSR
Speed mode 3, buffer off 6 20
All other speed modes 1 4
Offset error TA = 25°C, external short –1000 ±100 1000 µV
Offset drift 100 850 nV/°C
Gain error TA = 25°, including internal reference error, VREFP = 2.5V or 4.096V –1000 ±200 1000 ppm of FSR
TA = 25°, excluding reference error –150 ±50 150
Gain drift Including internal reference error, VREFP = 2.5V or 4.096V 5 13 ppm of FSR/°C
Excluding reference error 0.75 2
TUE Total Unadjusted Error Internal reference VREFP = 2.5 V 0.01 0.06 % FSR
Internal reference VREFP = 4.096 V 0.02 0.09
External reference VREFP = 2.5V or 4.096 V 0.01 0.03
SYSTEM PERFORMANCE
fDATA Output data rate, sinc3 or sinc4 filter Speed mode 3 (fMOD = 12.8 MHz) 0.08 1067 kSPS
Speed mode 2 (fMOD = 6.4 MHz) 0.04 533.3
Speed mode 1 (fMOD = 1.6 MHz) 0.01 133.3
Speed mode 0 (fMOD = 0.8 MHz) 0.005 66.7
NMRR Normal-mode rejection ratio, simultaneous 50/60Hz notch filter enabled fIN = 50 Hz or 60 Hz (±1 Hz), fDATA = 20 SPS,
external fCLK = 25.6 MHz		 –95.3 dB
fIN = 50 Hz or 60 Hz (±1 Hz), fDATA = 20 SPS,
internal fCLK = 25.6 MHz		 –82.7
fIN = 50 Hz or 60 Hz (±1 Hz), fDATA = 25 SPS,
external fCLK = 25.6 MHz		 –62.7
fIN = 50 Hz or 60 Hz (±1 Hz), fDATA = 25 SPS,
internal fCLK = 25.6 MHz		 –57.9
CMRR Common-mode rejection ratio At dc 110 dB
fCM = 50Hz or 60Hz (±1Hz), fDATA = 20SPS or
25SPS		 125
fCM = 50Hz or 60Hz (±1Hz), fDATA > 25SPS 90
PSRR Power-supply rejection ratio AVDD at dc 105 dB
IOVDD at dc 110
VOLTAGE REFERENCE INPUTS
REFP and REFN input current (REFN = AVSS) REFP buffer off Speed mode 3 190 µA/V
Speed mode 2 130
Speed mode 1 80
Speed mode 0 70
REFP input current REFP buffer on Speed mode 3 ±0.5 µA
Speed mode 2 ±0.3
Speed mode 1 ±0.1
Speed mode 0 ±0.1
REFP and REFN
input current drift		 REFP buffer off Speed mode 3 2.5 nA/℃
Speed mode 2 5
Speed mode 1 7
Speed mode 0 7.5
REFP input current drift REFP buffer on Speed mode 3 4 nA/℃
Speed mode 2 2.5
Speed mode 1 0.5
Speed mode 0 0.5
INTERNAL VOLTAGE REFERENCE
Output voltage AVDD > 4.5V,
REFOUT with respect to AVSS		 REF_VAL = 0b 2.5 V
REF_VAL = 1b 4.096
2.85V ≤ AVDD ≤ 4.5 V, 
REFOUT with respect to AVSS		 2.5
Initial accuracy TA = 25°C –0.1 ±0.02 0.1 %
Temperature drift(1) TA = 0°C to +125°C 4 12 ppm/°C
TA = –40°C to +125°C 4 12
Reference output load current Sink or source –10 10 mA
Short-circuit current limit Sink or source 25 40
Power supply rejection AVDD at DC 95 dB
Load regulation 50 ppm/mA
Voltage noise 0.1 to 10Hz, CL = 1µF VREF = 2.5 V 1.0 µVRMS
VREF = 4.096 V 1.7
Voltage noise density 1kHz, CL = 1µF VREF = 2.5 V 200 nV/√Hz
VREF = 4.096 V 300
Capacitive load 0.5 1 2 µF
Resistive load 2 kΩ
Start-up time From power-down mode, CL = 1 µF, 0.01% settling 1 1.5 ms
INTERNAL OSCILLATOR
fOSCM Frequency 25.6 MHz
Accuracy –0.75 0.07 0.75 %
TEMPERATURE SENSOR
TSOffset Output voltage TA = 25°C 120 mV
TSTC Temperature coefficient 400 µV/°C
Accuracy Speed mode 0, internal clock, OSR = 12, input buffers on –3 ±0.5 3 °C
MONITORS
THREF_UV Reference undervoltage threshold (2) 0.5 0.6 V
External reference voltage readback accuracy (VREFP – VREFN) / 3 ±0.5 %
Supply voltage readback accuracy AVDD / 3 ±1 %
DVDD / 3 ±1
(CAPA – AVSS) / 3 ±1
(CAPD – DGND) / 3 ±1
(RESP – RESN) / 3 ±1
OPEN-WIRE DETECTION CURRENT SOURCES AND SINKS
Current source settings 2, 8, 85 µA
Current sink settings 2, 8, 85 µA
Current source accuracy 85µA current setting ±2 %
All other current settings ±40
Current sink accuracy 85µA current setting ±2
All other current settings ±40
TEST DAC
Test DAC reference voltage AVDD ≥ 4.65 V TDAC_RANGE = 0b 2.5 V
TDAC_RANGE = 1b 4.096
2.85V ≤ AVDD ≤ 4.65 V   2.5
Resolution 5 Bits
Accuracy ±1 %
Offset error Measured by the line passing through two codes ±1 10 mV
Startup Time From rising edge of TDAC enable to DAC output voltage reaching 99% of its final value. Applies to the slowest DAC config (buffer or no buffer).  10 µs
Buffer output impedance Buffer shorted to ground with code = 11111, reference voltage = 4.096 V Buffer shorted to ground with code = 11111, reference voltage = 4.096 V 150 Ω
Buffer Load Current, Shorted Buffer shorted to ground with code = 11111, reference voltage = 4.096 V 15 mA
ANALOG GENERAL-PURPOSE INPUTS/OUTPUTS (GPIO)
VIL Logic input level, low 0.35 AVDD V
VIH Logic input level, high 0.65 AVDD V
VOL Logic output level, low IOL = 0.4 mA 0.45 AVDD V
VOH Logic output level, high IOH = –0.4 mA 0.6 AVDD V
Input hysteresis 30 mV
Input current –2 2 µA
DIGITAL INPUTS/OUTPUTS
VIL Logic input level, low DGND 0.3 × IOVDD V
VIH Logic input level, high 0.7 × IOVDD V
VOL Logic output level, low OUT_DRV = 0b, IOL = 2 mA 0.2 × IOVDD V
OUT_DRV = 1b, IOL = 1 mA 0.2 × IOVDD
VOH Logic output level, high OUT_DRV = 0b, IOH = –2 mA 0.8 × IOVDD V
OUT_DRV = 1b, IOH = –1 mA 0.8 × IOVDD
Input hysteresis 100 mV
Input current Excluding RESET pin –1 1 µA
RESET pin pullup resistor Internal pullup resistor 20 kΩ
ANALOG SUPPLY CURRENT
IAVDD, IAVSS AVDD and AVSS current
(All buffers off, internal reference off)		 Speed mode 3 6.5 7.5 mA
Speed mode 2 4 5
Speed mode 1 1.5 2
Speed mode 0 1.25 1.5
Standby mode 230 µA
Power-down mode 550 nA
AVDD and AVSS additional
current (per function)		 Input buffer Speed mode 3 2.5 3 mA/buffer
Speed mode 2 1.75 2
Speed mode 1 0.5 0.75
Speed mode 0 0.4 0.6
REFP buffer Speed mode 3 1.2 mA/buffer
Speed mode 2 0.8
Speed mode 1 0.3
Speed mode 0 0.25
Internal reference and reference buffer 100 200 µA
Test DAC, 2.5 V or 4.096 V range 700 µA
Test DAC buffer 800 µA
DIGITAL SUPPLY CURRENT
IIOVDD IOVDD current
 		 Speed mode 3, OSR = 32 0.9 1 mA
Speed mode 2, OSR = 32 0.5 0.6
Speed mode 1, OSR = 32 0.2 0.25
Speed mode 0, OSR = 32 0.12 0.2
Standby mode, external clock 5 µA
Standby mode, internal oscillator 60
Power-down mode 10
POWER DISSIPATION
PD Power dissipation AVDD = 5 V,
Input and REFP buffers off		 Speed mode 3 33 mW
Speed mode 2 20
Speed mode 1 6.6
Speed mode 0 6
(1) Specified by design and characterization, not production tested.
(2) Undervoltage monitor does always trip below the specified MIN value and does never trip above the specified MAX value.