SBASAE4 December   2025 ADS125P08

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 SFDR Measurement
    12. 6.12 Noise Performance
    13. 6.13 TUE (Total Unadjusted Error) Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Multiplexer
      2. 7.3.2  High-Impedance Input Buffers
      3. 7.3.3  Input Range
      4. 7.3.4  ADC Reference Voltage
      5. 7.3.5  Power Supplies
        1. 7.3.5.1 AVDD and AVSS
        2. 7.3.5.2 IOVDD
        3. 7.3.5.3 CAPA and CAPD
        4. 7.3.5.4 Power-On Reset (POR)
      6. 7.3.6  Clock Operation
        1. 7.3.6.1 Internal Oscillator
        2. 7.3.6.2 External Clock
      7. 7.3.7  Modulator
      8. 7.3.8  Digital Filter
        1. 7.3.8.1 Digital Filter Latency
        2. 7.3.8.2 Sinc3 and Sinc4 Filters
        3. 7.3.8.3 Sinc4 + Sinc1 Cascade Filter
        4. 7.3.8.4 50/60Hz Notch Filters
      9. 7.3.9  FIFO Buffer
        1. 7.3.9.1 FIFO Buffer Read and Write
        2. 7.3.9.2 FIFO Overflow and Underflow
        3. 7.3.9.3 FIFO Depth Indicator
        4. 7.3.9.4 FIFO Enable and Flush
        5. 7.3.9.5 FIFO Thresholds
      10. 7.3.10 Channel Auto-Sequencer
        1. 7.3.10.1 Auto-Sequencer: Basic Operation
        2. 7.3.10.2 Sequencer Modes
          1. 7.3.10.2.1 Single-Shot Mode
          2. 7.3.10.2.2 Single Step Continuous Conversion Mode
          3. 7.3.10.2.3 Single Sequence Mode
          4. 7.3.10.2.4 Continuous Sequence Mode
        3. 7.3.10.3 Configuring the Auto-Sequencer
        4. 7.3.10.4 Starting and Stopping the Sequencer
        5. 7.3.10.5 Auto-Sequencer and DRDY Behavior
      11. 7.3.11 Offset and Gain Calibration
      12. 7.3.12 General Purpose IOs (GPIOs)
        1. 7.3.12.1 DRDY Output
        2. 7.3.12.2 FAULT Output
      13. 7.3.13 Burn-Out Current Sources
      14. 7.3.14 Open Wire Detection with ADC 0-code output
      15. 7.3.15 System Monitors
        1. 7.3.15.1 Internal Short (Offset Calibration)
        2. 7.3.15.2 Internal Temperature Sensor
        3. 7.3.15.3 External Reference Voltage Readback
        4. 7.3.15.4 Power-Supply Readback
      16. 7.3.16 Monitor Flags, Indicators and Counters
        1. 7.3.16.1  Reset (RESETn flag)
        2. 7.3.16.2  AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.16.3  Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.16.4  Modulator Overrange Monitor (MOD_OVR_FAULTn flag)
        5. 7.3.16.5  Register Map CRC (REG_MAP_CRC_FAULTn flag)
        6. 7.3.16.6  Memory Map CRC (MEM_INTERNAL_FAULTn flag)
        7. 7.3.16.7  FIFO Overflow (FIFO_OFn flag) and FIFO Underflow (FIFO_UFn flag)
        8. 7.3.16.8  FIFO CRC Fault (FIFO_CRC_FAULTn flag)
        9. 7.3.16.9  GPIO Readback
        10. 7.3.16.10 SPI CRC Fault (SPI_CRC_FAULTn flag)
        11. 7.3.16.11 Register Write Fault (REG_WRITE_FAULTn flag)
        12. 7.3.16.12 DRDY Indicator (DRDY bit)
        13. 7.3.16.13 Sequencer Active Indicator (SEQ_ACTIVE bit)
        14. 7.3.16.14 Sequence Step Indicator (STEP_INDICATOR[4:0])
        15. 7.3.16.15 ADC Conversion Counter (CONV_COUNT[3:0])
        16. 7.3.16.16 FIFO Depth Indicator (FIFO_DEPTH[8:0])
        17. 7.3.16.17 Completed Sequence Counter (SEQ_COUNT[3:0])
      17. 7.3.17 Test DAC (TDAC)
      18. 7.3.18 Parallel Post Filters
        1. 7.3.18.1 Configuring the Parallel Post Filters
        2. 7.3.18.2 Frequency Response of the Parallel Post Filters
        3. 7.3.18.3 Settling Times and DRDY Behavior When Using the Post Filters
        4. 7.3.18.4 Examples of Recommended Post Filter Settings
      19. 7.3.19 Chip Select Forwarding
        1. 7.3.19.1 Configuring the CS forward feature
        2. 7.3.19.2 CS Forward Timeout
        3. 7.3.19.3 CS Forward Header, Frame, and State Diagram
        4. 7.3.19.4 Disabling the CS-FWD mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Scalable Speed Modes
      2. 7.4.2 Sequencer Functional Modes
      3. 7.4.3 Idle Mode and Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
      7. 7.4.7 Conversion-Start Delay Time
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No-Operation
        2. 7.5.4.2 Read Conversion Data
        3. 7.5.4.3 Read Register Command
        4. 7.5.4.4 Write Register Command
        5. 7.5.4.5 Read FIFO Buffer Command
      5. 7.5.5  Continuous Read Mode
        1. 7.5.5.1 Read Conversion Data in Continuous Read Mode
        2. 7.5.5.2 Read Registers in Continuous Read Mode
        3. 7.5.5.3 Read FIFO Buffer in Continuous Read Mode
      6. 7.5.6  SPI communication after POR or Reset
      7. 7.5.7  DRDY Pin Behavior
      8. 7.5.8  Daisy-Chain Operation
      9. 7.5.9  3-Wire SPI Mode
        1. 7.5.9.1 3-Wire SPI Mode Frame Re-Align
      10. 7.5.10 Conversion Data
      11. 7.5.11 Data Ready
        1. 7.5.11.1 DRDY Pin and SDO/DRDY Pin
        2. 7.5.11.2 DRDY Bit
        3. 7.5.11.3 Clock Counting
    6. 7.6 Register Map
      1. 7.6.1 ADS125P08 Status and General Configuration Page
      2. 7.6.2 ADS125P08 Step Configuration Page
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Serial Interface Connections
      2. 8.1.2 Interfacing with Multiple Devices
      3. 8.1.3 Unused Inputs and Outputs
      4. 8.1.4 Device Initialization
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plots - Crosstalk
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supplies
      2. 8.3.2 Power-Supply Sequencing
      3. 8.3.3 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.8.2 Sinc3 and Sinc4 Filters

The sinc filter averages and decimates the high-speed modulator data to produce high-resolution output data at reduced data rate. Increasing the OSR value decreases the data rate and simultaneously reduces signal bandwidth and conversion noise resulting from increased decimation and data averaging. Table 7-15 lists the sinc3 and sinc4 filter –3dB frequencies and latency times. The latency times (shown in μs) are given for the nominal clock frequencies, and the values scale with the clock frequency.

Table 7-9 Sinc3 and Sinc4 Filter Characteristics
SPEED

MODE

 fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 –3dB FREQUENCY (kHz) LATENCY TIME (μs)
SINC3 SINC4 SINC3 SINC4
3 25.6 12 1066.67 279.5 242.3 3.9 4.8
2 12.8 533.33 139.7 121.2 7.7 9.6
1 3.2 133.33 34.9 30.3 30.9 38.4
0 1.6 66.67 17.5 15.1 61.9 76.9
3 25.6 16 800 209.6 181.8 4.8 6.1
2 12.8 400 104.8 90.9 9.6 12.1
1 3.2 100 26.2 22.7 38.4 48.4
0 1.6 50 13.1 11.4 76.9 96.9
3 25.6 24 533.33 139.7 121.2 6.7 8.6
2 12.8 266.67 69.9 60.6 13.4 17.1
1 3.2 66.67 17.5 15.1 53.4 68.4
0 1.6 33.33 8.7 7.6 106.9 136.9
3 25.6 32 400 104.8 90.9 8.6 11.1
2 12.8 200 52.4 45.4 17.1 22.1
1 3.2 50 13.1 11.4 68.4 88.4
0 1.6 25 6.6 5.7 136.9 176.9
3 25.6 64 200 52.4 45.4 16.1 21.1
2 12.8 100 26.2 22.7 32.1 42.1
1 3.2 25 6.6 5.7 128.4 168.4
0 1.6 12.5 3.3 2.8 256.9 336.9
3 25.6 128 100 26.2 22.7 31.1 41.1
2 12.8 50 13.1 11.4 62.1 82.1
1 3.2 12.5 3.3 2.8 248.4 328.4
0 1.6 6.25 1.6 1.4 496.9 656.9
3 25.6 256 50 13.1 11.36 61.1 81.1
2 12.8 25 6.55 5.68 122.1 162.1
1 3.2 6.25 1.64 1.42 488.4 648.4
0 1.6 3.13 0.82 0.71 976.9 1296.9
3 25.6 512 25 6.55 5.68 121.1 161.1
2 12.8 12.5 3.28 2.84 242.1 322.1
1 3.2 3.13 0.82 0.71 968.4 1288.4
0 1.6 1.56 0.41 0.35 1936.9 2576.9
3 25.6 1024 12.5 3.28 2.84 241.1 321.1
2 12.8 6.25 1.64 1.42 482.1 642.1
1 3.2 1.56 0.41 0.35 1928.4 2568.4
0 1.6 0.78 0.204 0.177 3856.9 5136.9
3 25.6 2048 6.25 1.638 1.42 481.1 641.1
2 12.8 3.13 0.82 0.711 962.1 1282.1
1 3.2 0.78 0.204 0.177 3848.4 5128.4
0 1.6 0.39 0.102 0.089 7696.9 10256.9
3 25.6 4000 3.2 0.838 0.727 938.6 1251.1
2 12.8 1.6 0.419 0.364 1877.1 2502.1
1 3.2 0.4 0.105 0.091 7508.4 10008.4
0 1.6 0.2 0.052 0.045 15016.9 20016.9
3 25.6 8000 1.6 0.419 0.364 1876.1 2501.1
2 12.8 0.8 0.21 0.182 3752.1 5002.1
1 3.2 0.2 0.052 0.045 15008.4 20008.4
0 1.6 0.1 0.026 0.023 30016.9 40016.9
3 25.6 16000 0.8 0.21 0.182 3751.1 5001.1
2 12.8 0.4 0.105 0.091 7502.1 10002.1
1 3.2 0.1 0.026 0.023 30008.4 40008.4
0 1.6 0.05 0.013 0.011 60016.9 80016.9
3 25.6 26667 0.48 0.126 0.109 6251.1 8334.5
2 12.8 0.24 0.063 0.055 12502.3 16669
1 3.2 0.06 0.016 0.014 50009.1 66675.9
0 1.6 0.03 0.008 0.007 100018.1 133351.9
3 25.6 32000 0.4 0.105 0.091 7501.1 10001.1
2 12.8 0.2 0.052 0.045 15002.1 20002.1
1 3.2 0.05 0.013 0.011 60008.4 80008.4
0 1.6 0.03 0.008 0.007 120016.9 160016.9
3 25.6 96000 0.13 0.034 0.03 22501.1 30001.1
2 12.8 0.07 0.018 0.016 45002.1 60002.1
1 3.2 0.02 0.005 0.005 180008.4 240008.4
0 1.6 0.008 0.002 0.002 360016.9 480016.9
3 25.6 160000 0.08 0.021 0.018 37501.1 50001.1
2 12.8 0.04 0.01 0.009 75002.1 100002.1
1 3.2 0.01 0.003 0.002 300008.4 400008.4
0 1.6 0.005 0.001 0.001 600016.9 800016.9

Figure 7-12 and Figure 7-13 show the sinc filter frequency response. The frequency response consists of a series of response nulls occurring at fDATA and multiples thereof. At the null frequencies, the filter has zero gain. Figure 7-13 shows the folding of the frequency response starting at fMOD / 2. No attenuation is provided by the filter at input frequencies near n × fMOD (n = 1, 2, 3, and so on).

ADS125P08 Sinc3 and Sinc4 Frequency Response Figure 7-12 Sinc3 and Sinc4 Frequency Response
ADS125P08 Sinc4 Frequency Response to fMOD (OSR = 32)Figure 7-13 Sinc4 Frequency Response to fMOD (OSR = 32)

Table 7-10 shows the normal-mode rejection of a few selected filter settings for data rates equal to common line-cycle frequencies.

Table 7-10 Normal-Mode Rejection
SPEED

MODE

(1)		 OSR fDATA (SPS) DIGITAL FILTER Response (dB)
2% CLOCK VARIATION 6% CLOCK VARIATION
SINC3 FILTER SINC4 FILTER SINC3 FILTER SINC4 FILTER
1 96000 16.6 –100dB –135dB –72dB –95dB
1 32000 50
1 26667 60
1 8000 200
1 4000 400
(1) Nominal clock frequency for each speed mode is used: fCLK = 25.6MHz (speed mode 3), 12.8MHz (speed mode 2), 3.2MHz (speed mode 1), 1.6MHz (speed mode 0).

If the ADC connection leads are in close proximity to industrial motors and conductors, coupling of 50Hz and 60Hz power line frequencies can occur. The coupled noise interferes with the signal voltage, and can lead to inaccurate or unstable conversions. The digital filter provides enhanced rejection of power-line coupled noise for data rates of 60 SPS and less. Program the filter to tradeoff data rate and conversion latency versus the desired level of line cycle rejection. Table 7-14 summarizes the 50Hz and 60Hz line-cycle rejection based on ±1Hz tolerance of power-line to ADC clock frequency, and additional clock tolerance of 0% (e.g. external clock) and 1% (e.g. internal clock). Best possible power line rejection is provided by the high-order sinc filter and by using an accurate ADC clock.

Table 7-11 50Hz and 60Hz Line Cycle Rejection
SPEED

MODE

(1)		 OSR Filter type fDATA (SPS) DIGITAL FILTER RESPONSE (dB)
50Hz ±1Hz 60Hz ±1Hz
CLOCK TOLERANCE: (2)
0% 1% 0% 1%
0 160000 Sinc4 5 -137.5 -126.1 -144.0 -131.0
0 160000 Sinc3 5 -103.1 -94.6 -108.0 -98.3
1 160000 Sinc4 10 -135.8 -122.1 -142.2 -126.5
1 160000 Sinc3 10 -101.8 -91.6 -106.7 -94.8
1 96000 Sinc4 16.6 -135.4 -121.2 -84.0 -83.3
1 96000 Sinc3 16.6 -101.6 -90.9 -63.0 -62.5
0 32000 Sinc4 25 -135.3 -121.0 -71.4 -71.3
0 32000 Sinc3 25 -101.5 -90.7 -53.5 -53.5
1 32000 Sinc4 50 -135.2 -120.8 -62.3 -61.1
1 32000 Sinc3 50 -101.4 -90.6 -46.7 -45.9
1 26667 Sinc4 60 -53.8 -52.1 -141.7 -125.0
1 26667 Sinc3 60 -40.4 -39.1 -106.3 -93.8
0 16000 Sinc4 50 -135.2 -120.8 -62.3 -61.1
0 16000 Sinc3 50 -101.4 -90.6 -46.7 -45.9
(1) Nominal clock frequency for each speed mode is used: fCLK = 25.6MHz (speed mode 3), 12.8MHz (speed mode 2), 3.2MHz (speed mode 1), 1.6MHz (speed mode 0).
(2) 0% clock tolerance corresponds to external clock, 1% clock tolerance corresponds to internal clock.