SBASAE4 December   2025 ADS125P08

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 SFDR Measurement
    12. 6.12 Noise Performance
    13. 6.13 TUE (Total Unadjusted Error) Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Multiplexer
      2. 7.3.2  High-Impedance Input Buffers
      3. 7.3.3  Input Range
      4. 7.3.4  ADC Reference Voltage
      5. 7.3.5  Power Supplies
        1. 7.3.5.1 AVDD and AVSS
        2. 7.3.5.2 IOVDD
        3. 7.3.5.3 CAPA and CAPD
        4. 7.3.5.4 Power-On Reset (POR)
      6. 7.3.6  Clock Operation
        1. 7.3.6.1 Internal Oscillator
        2. 7.3.6.2 External Clock
      7. 7.3.7  Modulator
      8. 7.3.8  Digital Filter
        1. 7.3.8.1 Digital Filter Latency
        2. 7.3.8.2 Sinc3 and Sinc4 Filters
        3. 7.3.8.3 Sinc4 + Sinc1 Cascade Filter
        4. 7.3.8.4 50/60Hz Notch Filters
      9. 7.3.9  FIFO Buffer
        1. 7.3.9.1 FIFO Buffer Read and Write
        2. 7.3.9.2 FIFO Overflow and Underflow
        3. 7.3.9.3 FIFO Depth Indicator
        4. 7.3.9.4 FIFO Enable and Flush
        5. 7.3.9.5 FIFO Thresholds
      10. 7.3.10 Channel Auto-Sequencer
        1. 7.3.10.1 Auto-Sequencer: Basic Operation
        2. 7.3.10.2 Sequencer Modes
          1. 7.3.10.2.1 Single-Shot Mode
          2. 7.3.10.2.2 Single Step Continuous Conversion Mode
          3. 7.3.10.2.3 Single Sequence Mode
          4. 7.3.10.2.4 Continuous Sequence Mode
        3. 7.3.10.3 Configuring the Auto-Sequencer
        4. 7.3.10.4 Starting and Stopping the Sequencer
        5. 7.3.10.5 Auto-Sequencer and DRDY Behavior
      11. 7.3.11 Offset and Gain Calibration
      12. 7.3.12 General Purpose IOs (GPIOs)
        1. 7.3.12.1 DRDY Output
        2. 7.3.12.2 FAULT Output
      13. 7.3.13 Burn-Out Current Sources
      14. 7.3.14 Open Wire Detection with ADC 0-code output
      15. 7.3.15 System Monitors
        1. 7.3.15.1 Internal Short (Offset Calibration)
        2. 7.3.15.2 Internal Temperature Sensor
        3. 7.3.15.3 External Reference Voltage Readback
        4. 7.3.15.4 Power-Supply Readback
      16. 7.3.16 Monitor Flags, Indicators and Counters
        1. 7.3.16.1  Reset (RESETn flag)
        2. 7.3.16.2  AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.16.3  Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.16.4  Modulator Overrange Monitor (MOD_OVR_FAULTn flag)
        5. 7.3.16.5  Register Map CRC (REG_MAP_CRC_FAULTn flag)
        6. 7.3.16.6  Memory Map CRC (MEM_INTERNAL_FAULTn flag)
        7. 7.3.16.7  FIFO Overflow (FIFO_OFn flag) and FIFO Underflow (FIFO_UFn flag)
        8. 7.3.16.8  FIFO CRC Fault (FIFO_CRC_FAULTn flag)
        9. 7.3.16.9  GPIO Readback
        10. 7.3.16.10 SPI CRC Fault (SPI_CRC_FAULTn flag)
        11. 7.3.16.11 Register Write Fault (REG_WRITE_FAULTn flag)
        12. 7.3.16.12 DRDY Indicator (DRDY bit)
        13. 7.3.16.13 Sequencer Active Indicator (SEQ_ACTIVE bit)
        14. 7.3.16.14 Sequence Step Indicator (STEP_INDICATOR[4:0])
        15. 7.3.16.15 ADC Conversion Counter (CONV_COUNT[3:0])
        16. 7.3.16.16 FIFO Depth Indicator (FIFO_DEPTH[8:0])
        17. 7.3.16.17 Completed Sequence Counter (SEQ_COUNT[3:0])
      17. 7.3.17 Test DAC (TDAC)
      18. 7.3.18 Parallel Post Filters
        1. 7.3.18.1 Configuring the Parallel Post Filters
        2. 7.3.18.2 Frequency Response of the Parallel Post Filters
        3. 7.3.18.3 Settling Times and DRDY Behavior When Using the Post Filters
        4. 7.3.18.4 Examples of Recommended Post Filter Settings
      19. 7.3.19 Chip Select Forwarding
        1. 7.3.19.1 Configuring the CS forward feature
        2. 7.3.19.2 CS Forward Timeout
        3. 7.3.19.3 CS Forward Header, Frame, and State Diagram
        4. 7.3.19.4 Disabling the CS-FWD mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Scalable Speed Modes
      2. 7.4.2 Sequencer Functional Modes
      3. 7.4.3 Idle Mode and Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
      7. 7.4.7 Conversion-Start Delay Time
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No-Operation
        2. 7.5.4.2 Read Conversion Data
        3. 7.5.4.3 Read Register Command
        4. 7.5.4.4 Write Register Command
        5. 7.5.4.5 Read FIFO Buffer Command
      5. 7.5.5  Continuous Read Mode
        1. 7.5.5.1 Read Conversion Data in Continuous Read Mode
        2. 7.5.5.2 Read Registers in Continuous Read Mode
        3. 7.5.5.3 Read FIFO Buffer in Continuous Read Mode
      6. 7.5.6  SPI communication after POR or Reset
      7. 7.5.7  DRDY Pin Behavior
      8. 7.5.8  Daisy-Chain Operation
      9. 7.5.9  3-Wire SPI Mode
        1. 7.5.9.1 3-Wire SPI Mode Frame Re-Align
      10. 7.5.10 Conversion Data
      11. 7.5.11 Data Ready
        1. 7.5.11.1 DRDY Pin and SDO/DRDY Pin
        2. 7.5.11.2 DRDY Bit
        3. 7.5.11.3 Clock Counting
    6. 7.6 Register Map
      1. 7.6.1 ADS125P08 Status and General Configuration Page
      2. 7.6.2 ADS125P08 Step Configuration Page
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Serial Interface Connections
      2. 8.1.2 Interfacing with Multiple Devices
      3. 8.1.3 Unused Inputs and Outputs
      4. 8.1.4 Device Initialization
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plots - Crosstalk
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supplies
      2. 8.3.2 Power-Supply Sequencing
      3. 8.3.3 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)

SDO/DRDY is a dual-function output pin. This pin is programmable to provide output data only, or to provide output data and the data-ready indication. The SDO_MODE bit of the CLK_DIGITAL_CFG register programs the mode. The dual-function mode multiplexes output data and data-ready operations on a single pin. This mode can replace the function of the dedicated DRDY pin to reduce the number of SPI I/O lines required to interface to the host.

Output data update on the rising edge of SCLK. The SDO/DRDY pin is in a high-impedance state when CS is high.

When programmed to dual-function mode (SDO_MODE bit = 1b) and when CS is low, SDO/DRDY mirrors DRDY until the first rising edge of SCLK, at which time the pin changes mode to provide data output. When the data read operation is complete (24th falling edge of SCLK, or 48th edge if the CRC byte and STATUS header are included), the pin reverts back to mirroring DRDY. Figure 7-41 illustrates the operation of SDO/DRDY.

When using the dual-function mode of ADS125P08, the device switches from DRDY to SDO mode at the first rising SCLK. This transition takes tp(DRDO) which must be accounted for either by lengthening the first SCLK high-period, lengthening all SCLK high-periods, or latching output data after SCLK falling edge.

ADS125P08 SDO/DRDY and DRDY Function Figure 7-41 SDO/DRDY and DRDY Function

For the output data only mode SDO_MODE = 0b, SDO stays at the level of the last bit sent if the host does not send any extra SCLK pulses after the last data is shifted out on SDO, as shown in Figure 7-41. If the host sends additional SCLK pulses after the last data is shifted out, then SDO drives low. Figure 7-42 shows a timing diagram of the SDO behavior with additional SCLK pulses.

ADS125P08 SDO/DRDY and DRDY Function With Additional SCLK Pulses Figure 7-42 SDO/DRDY and DRDY Function With Additional SCLK Pulses