SBASAE4 December   2025 ADS125P08

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 SFDR Measurement
    12. 6.12 Noise Performance
    13. 6.13 TUE (Total Unadjusted Error) Measurement
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Multiplexer
      2. 7.3.2  High-Impedance Input Buffers
      3. 7.3.3  Input Range
      4. 7.3.4  ADC Reference Voltage
      5. 7.3.5  Power Supplies
        1. 7.3.5.1 AVDD and AVSS
        2. 7.3.5.2 IOVDD
        3. 7.3.5.3 CAPA and CAPD
        4. 7.3.5.4 Power-On Reset (POR)
      6. 7.3.6  Clock Operation
        1. 7.3.6.1 Internal Oscillator
        2. 7.3.6.2 External Clock
      7. 7.3.7  Modulator
      8. 7.3.8  Digital Filter
        1. 7.3.8.1 Digital Filter Latency
        2. 7.3.8.2 Sinc3 and Sinc4 Filters
        3. 7.3.8.3 Sinc4 + Sinc1 Cascade Filter
        4. 7.3.8.4 50/60Hz Notch Filters
      9. 7.3.9  FIFO Buffer
        1. 7.3.9.1 FIFO Buffer Read and Write
        2. 7.3.9.2 FIFO Overflow and Underflow
        3. 7.3.9.3 FIFO Depth Indicator
        4. 7.3.9.4 FIFO Enable and Flush
        5. 7.3.9.5 FIFO Thresholds
      10. 7.3.10 Channel Auto-Sequencer
        1. 7.3.10.1 Auto-Sequencer: Basic Operation
        2. 7.3.10.2 Sequencer Modes
          1. 7.3.10.2.1 Single-Shot Mode
          2. 7.3.10.2.2 Single Step Continuous Conversion Mode
          3. 7.3.10.2.3 Single Sequence Mode
          4. 7.3.10.2.4 Continuous Sequence Mode
        3. 7.3.10.3 Configuring the Auto-Sequencer
        4. 7.3.10.4 Starting and Stopping the Sequencer
        5. 7.3.10.5 Auto-Sequencer and DRDY Behavior
      11. 7.3.11 Offset and Gain Calibration
      12. 7.3.12 General Purpose IOs (GPIOs)
        1. 7.3.12.1 DRDY Output
        2. 7.3.12.2 FAULT Output
      13. 7.3.13 Burn-Out Current Sources
      14. 7.3.14 Open Wire Detection with ADC 0-code output
      15. 7.3.15 System Monitors
        1. 7.3.15.1 Internal Short (Offset Calibration)
        2. 7.3.15.2 Internal Temperature Sensor
        3. 7.3.15.3 External Reference Voltage Readback
        4. 7.3.15.4 Power-Supply Readback
      16. 7.3.16 Monitor Flags, Indicators and Counters
        1. 7.3.16.1  Reset (RESETn flag)
        2. 7.3.16.2  AVDD Undervoltage Monitor (AVDD_UVn flag)
        3. 7.3.16.3  Reference Undervoltage Monitor (REV_UVn flag)
        4. 7.3.16.4  Modulator Overrange Monitor (MOD_OVR_FAULTn flag)
        5. 7.3.16.5  Register Map CRC (REG_MAP_CRC_FAULTn flag)
        6. 7.3.16.6  Memory Map CRC (MEM_INTERNAL_FAULTn flag)
        7. 7.3.16.7  FIFO Overflow (FIFO_OFn flag) and FIFO Underflow (FIFO_UFn flag)
        8. 7.3.16.8  FIFO CRC Fault (FIFO_CRC_FAULTn flag)
        9. 7.3.16.9  GPIO Readback
        10. 7.3.16.10 SPI CRC Fault (SPI_CRC_FAULTn flag)
        11. 7.3.16.11 Register Write Fault (REG_WRITE_FAULTn flag)
        12. 7.3.16.12 DRDY Indicator (DRDY bit)
        13. 7.3.16.13 Sequencer Active Indicator (SEQ_ACTIVE bit)
        14. 7.3.16.14 Sequence Step Indicator (STEP_INDICATOR[4:0])
        15. 7.3.16.15 ADC Conversion Counter (CONV_COUNT[3:0])
        16. 7.3.16.16 FIFO Depth Indicator (FIFO_DEPTH[8:0])
        17. 7.3.16.17 Completed Sequence Counter (SEQ_COUNT[3:0])
      17. 7.3.17 Test DAC (TDAC)
      18. 7.3.18 Parallel Post Filters
        1. 7.3.18.1 Configuring the Parallel Post Filters
        2. 7.3.18.2 Frequency Response of the Parallel Post Filters
        3. 7.3.18.3 Settling Times and DRDY Behavior When Using the Post Filters
        4. 7.3.18.4 Examples of Recommended Post Filter Settings
      19. 7.3.19 Chip Select Forwarding
        1. 7.3.19.1 Configuring the CS forward feature
        2. 7.3.19.2 CS Forward Timeout
        3. 7.3.19.3 CS Forward Header, Frame, and State Diagram
        4. 7.3.19.4 Disabling the CS-FWD mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Scalable Speed Modes
      2. 7.4.2 Sequencer Functional Modes
      3. 7.4.3 Idle Mode and Standby Mode
      4. 7.4.4 Power-Down Mode
      5. 7.4.5 Reset
        1. 7.4.5.1 RESET Pin
        2. 7.4.5.2 Reset by SPI Register Write
        3. 7.4.5.3 Reset by SPI Input Pattern
      6. 7.4.6 Synchronization
      7. 7.4.7 Conversion-Start Delay Time
    5. 7.5 Programming
      1. 7.5.1  Serial Interface (SPI)
      2. 7.5.2  Serial Interface Signals
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output/Data Ready (SDO/DRDY)
        5. 7.5.2.5 Data Ready (DRDY) Pin
      3. 7.5.3  Serial Interface Communication Structure
        1. 7.5.3.1 SPI Frame
        2. 7.5.3.2 STATUS Header
        3. 7.5.3.3 SPI CRC
      4. 7.5.4  Device Commands
        1. 7.5.4.1 No-Operation
        2. 7.5.4.2 Read Conversion Data
        3. 7.5.4.3 Read Register Command
        4. 7.5.4.4 Write Register Command
        5. 7.5.4.5 Read FIFO Buffer Command
      5. 7.5.5  Continuous Read Mode
        1. 7.5.5.1 Read Conversion Data in Continuous Read Mode
        2. 7.5.5.2 Read Registers in Continuous Read Mode
        3. 7.5.5.3 Read FIFO Buffer in Continuous Read Mode
      6. 7.5.6  SPI communication after POR or Reset
      7. 7.5.7  DRDY Pin Behavior
      8. 7.5.8  Daisy-Chain Operation
      9. 7.5.9  3-Wire SPI Mode
        1. 7.5.9.1 3-Wire SPI Mode Frame Re-Align
      10. 7.5.10 Conversion Data
      11. 7.5.11 Data Ready
        1. 7.5.11.1 DRDY Pin and SDO/DRDY Pin
        2. 7.5.11.2 DRDY Bit
        3. 7.5.11.3 Clock Counting
    6. 7.6 Register Map
      1. 7.6.1 ADS125P08 Status and General Configuration Page
      2. 7.6.2 ADS125P08 Step Configuration Page
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Serial Interface Connections
      2. 8.1.2 Interfacing with Multiple Devices
      3. 8.1.3 Unused Inputs and Outputs
      4. 8.1.4 Device Initialization
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plots - Crosstalk
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supplies
      2. 8.3.2 Power-Supply Sequencing
      3. 8.3.3 Power-Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.12 Noise Performance

Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between modulator frequency and output data rate is called the oversampling ratio (OSR). By increasing the OSR, and thus reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the input-referred noise drops when reducing the output data rate because more samples of the internal modulator are averaged to yield one conversion result.

The ADC provides four speed modes that allow trade-offs between ADC resolution, power consumption, and signal bandwidth. The modes are speed mode 3, speed mode 2, speed mode 1 and speed mode 0, with decreasing orders of device power consumption.

The digital filter provides the options of sinc3, sinc4, and sinc4 + sinc1 configurations. The sinc3 and sinc4 filters offer data rates up to 1.066MSPS in speed mode 3, up to 533kSPS in speed mode 2, up to 133kSPS in speed mode 1 and up to 66.67kSPS in speed mode 0. The device also offers custom 20SPS and 25SPS filter modes with simultaneous 50Hz/60Hz rejection.

The following tables in this section summarize the noise performance and resulting effective resolution of the various filter modes. Noise performance is shown for a 2.5V and a 4.096V reference voltage. In general, decreasing the reference voltage from 4.096V to 2.5V decreases dynamic range by 4dB (typical).

The data shown are typical input-referred noise results (en(RMS)) in units of μVRMS with the analog inputs shorted together and are representative of typical performance at TA = 25°C. A minimum of 1,000 or 10 seconds of consecutive conversions (whichever occurs first) are used to measure RMS noise (en(RMS)). Because of the statistical nature of noise, repeated noise measurements can yield higher or lower noise results.

Equation 12 or Equation 13 calculate effective resolution from the measured μVRMS numbers, depending on the selected coding scheme.

Equation 12. Effective ResolutionBinary two's complement coding = ln[(FSR / en(RMS)] / ln(2)
Equation 13. Effective ResolutionUnipolar straight binary coding = ln[(0.5 × FSR) / en(RMS)] / ln(2)

where:

  • FSR = 2 × VREF
  • en(RMS) = Noise voltage (RMS)

Note that all values in this section are generated using the ±10V input range, thus FSR = 20V.

Input-referred noise (en) in units of μVPP can be estimated as en(PP) = 6.6 × en(RMS). Use Equation 14 or Equation 15 to calculate noise-free resolution from the estimated μVPP numbers, depending on the selected coding scheme.

Equation 14. Noise-free ResolutionBinary two's complement coding = ln[FSR / en(PP)] / ln(2)
Equation 15. Noise-free ResolutionUnipolar straight binary coding = ln[(0.5 × FSR) / en(PP)] / ln(2)

When evaluating ADC noise performance, consider the effect of external components to the total noise performance. The noise performance of the ADC can be evaluated in isolation by selecting the input short test connection of the input multiplexer.

Table 6-1 Sinc3 and Sinc4 Filter Noise Performance (VREF = 2.5V)
OSR DATA RATE
(kSPS)		 NOISE
(en(RMS), µVRMS)(1)		 EFFECTIVE RESOLUTION ±2.5V RANGE (Bits)
SINC3 SINC4 SINC3 SINC4
SPEED MODE 3 (fMOD =12.8MHz)
12 1066.67 146.67 41.20 15.1 16.9
16 800.00 62.88 17.52 16.3 18.1
24 533.33 20.41 9.52 17.9 19.0
32 400.00 11.22 7.71 18.8 19.3
64 200.00 5.85 5.34 19.7 19.8
128 100.00 4.06 3.76 20.2 20.3
256 50.00 2.92 2.68 20.7 20.8
512 25.00 1.98 1.88 21.3 21.3
1,024 12.50 1.41 1.35 21.8 21.8
2,048 6.25 1.03 0.97 22.2 22.3
4,000 3.20 0.75 0.69 22.7 22.8
8,000 1.60 0.55 0.51 23.1 23.2
16,000 0.80 0.41 0.39 23.5 23.6
26,667 0.48 0.39 0.35 23.6 23.8
32,000 0.40 0.35 0.37 23.8 23.7
96,000 0.13 0.34 0.26 23.8 24.2
160,000 0.08 0.25 0.27 24.3 24.1
SPEED MODE 2 (fMOD =12.8MHz)
12 533.33 148.06 41.26 15.0 16.9
16 400.00 62.62 17.28 16.3 18.1
24 266.67 20.22 9.31 17.9 19.0
32 200.00 10.94 7.46 18.8 19.4
64 100.00 5.69 5.23 19.7 19.9
128 50.00 3.92 3.70 20.3 20.4
256 25.00 2.76 2.59 20.8 20.9
512 12.50 2.01 1.86 21.2 21.4
1,024 6.25 1.38 1.34 21.8 21.8
2,048 3.13 1.00 0.93 22.3 22.4
4,000 1.60 0.72 0.67 22.7 22.8
8,000 0.80 0.50 0.49 23.3 23.3
16,000 0.40 0.37 0.35 23.7 23.8
26,667 0.24 0.30 0.29 24.0 24.0
32,000 0.20 0.28 0.26 24.1 24.2
96,000 0.07 0.18 0.17 24.7 24.8
160,000 0.04 0.15 0.15 25.0 25.0
SPEED MODE 1 (fMOD =1.6MHz)
12 533.33 148.02 40.24 15.0 16.9
16 400.00 63.02 17.53 16.3 18.1
24 266.67 20.45 9.18 17.9 19.1
32 200.00 11.23 7.57 18.8 19.3
64 100.00 5.61 5.17 19.8 19.9
128 50.00 3.89 3.64 20.3 20.4
256 25.00 2.75 2.56 20.8 20.9
512 12.50 1.95 1.83 21.3 21.4
1,024 6.25 1.38 1.30 21.8 21.9
2,048 3.13 0.96 0.93 22.3 22.4
4,000 1.60 0.71 0.66 22.7 22.9
8,000 0.80 0.51 0.49 23.2 23.3
16,000 0.40 0.38 0.36 23.6 23.7
26,667 0.24 0.31 0.28 23.9 24.1
32,000 0.20 0.28 0.26 24.1 24.2
96,000 0.07 0.19 0.19 24.6 24.6
160,000 0.04 0.18 0.15 24.7 25.0
SPEED MODE 0 (fMOD =0.8MHz)
12 533.33 147.24 40.20 15.1 16.9
16 400.00 62.46 16.98 16.3 18.2
24 266.67 20.56 9.21 17.9 19.1
32 200.00 10.94 7.42 18.8 19.4
64 100.00 5.60 5.19 19.8 19.9
128 50.00 3.92 3.72 20.3 20.4
256 25.00 2.78 2.55 20.8 20.9
512 12.50 1.98 1.79 21.3 21.4
1,024 6.25 1.36 1.32 21.8 21.9
2,048 3.13 0.96 0.91 22.3 22.4
4,000 1.60 0.71 0.66 22.7 22.9
8,000 0.80 0.50 0.47 23.3 23.3
16,000 0.40 0.35 0.33 23.8 23.9
26,667 0.24 0.29 0.29 24.0 24.0
32,000 0.20 0.25 0.25 24.3 24.3
96,000 0.07 0.19 0.17 24.6 24.8
160,000 0.04 0.15 0.15 25.0 25.0
(1) High OSR values can yield varying noise results because of the limits of 24-bit quantization: 2.5V / 223 = 0.298μV / code.
Table 6-2 Sinc3 and Sinc4 Filter Noise Performance (VREF = 4.096V)
OSR DATA RATE
(kSPS)		 NOISE
(en(RMS), µVRMS)(1)		 EFFECTIVE RESOLUTION ±4.096V RANGE (Bits)
SINC3 SINC4 SINC3 SINC4
SPEED MODE 3 (fMOD =12.8MHz)
12 1066.67 240.01 64.46 15.1 17.0
16 800.00 101.48 24.34 16.3 18.4
24 533.33 30.98 10.36 18.0 19.6
32 400.00 15.13 8.19 19.0 19.9
64 200.00 6.14 5.54 20.3 20.5
128 100.00 4.16 3.93 20.9 21.0
256 50.00 2.92 2.77 21.4 21.5
512 25.00 2.09 1.97 21.9 22.0
1,024 12.50 1.47 1.36 22.4 22.5
2,048 6.25 1.04 0.99 22.9 23.0
4,000 3.20 0.79 0.74 23.3 23.4
8,000 1.60 0.58 0.56 23.8 23.8
16,000 0.80 0.45 0.44 24.1 24.2
26,667 0.48 0.39 0.41 24.3 24.3
32,000 0.40 0.39 0.37 24.3 24.4
96,000 0.13 0.35 0.36 24.5 24.4
160,000 0.08 0.32 0.31 24.6 24.7
SPEED MODE 2 (fMOD =12.8MHz)
12 1066.67 236.10 65.35 15.1 16.9
16 800.00 101.12 24.12 16.3 18.4
24 533.33 30.74 10.15 18.0 19.6
32 400.00 14.93 7.78 19.1 20.0
64 200.00 6.04 5.40 20.4 20.5
128 100.00 4.08 3.69 20.9 21.1
256 50.00 2.84 2.68 21.5 21.5
512 25.00 2.04 1.89 21.9 22.0
1,024 12.50 1.44 1.37 22.4 22.5
2,048 6.25 1.02 0.96 22.9 23.0
4,000 3.20 0.74 0.70 23.4 23.5
8,000 1.60 0.54 0.51 23.9 23.9
16,000 0.80 0.40 0.37 24.3 24.4
26,667 0.48 0.33 0.32 24.6 24.6
32,000 0.40 0.31 0.29 24.7 24.8
96,000 0.13 0.19 0.19 25.4 25.4
160,000 0.08 0.19 0.19 25.4 25.4
SPEED MODE 1 (fMOD =1.6MHz)
12 1066.67 241.10 63.37 15.1 17.0
16 800.00 99.71 24.14 16.3 18.4
24 533.33 30.61 10.22 18.0 19.6
32 400.00 15.05 7.88 19.1 20.0
64 200.00 5.91 5.36 20.4 20.5
128 100.00 4.01 3.80 21.0 21.0
256 50.00 2.81 2.65 21.5 21.6
512 25.00 2.02 1.86 22.0 22.1
1,024 12.50 1.38 1.29 22.5 22.6
2,048 6.25 1.02 0.95 22.9 23.0
4,000 3.20 0.73 0.66 23.4 23.6
8,000 1.60 0.53 0.51 23.9 23.9
16,000 0.80 0.41 0.39 24.3 24.3
26,667 0.48 0.32 0.33 24.6 24.6
32,000 0.40 0.30 0.30 24.7 24.7
96,000 0.13 0.24 0.23 25.0 25.1
160,000 0.08 0.22 0.24 25.2 25.0
SPEED MODE 0 (fMOD =0.8MHz)
12 1066.67 235.34 63.38 15.1 17.0
16 800.00 100.08 23.57 16.3 18.4
24 533.33 31.39 10.32 18.0 19.6
32 400.00 15.03 7.72 19.1 20.0
64 200.00 5.89 5.39 20.4 20.5
128 100.00 3.94 3.75 21.0 21.1
256 50.00 2.78 2.61 21.5 21.6
512 25.00 1.96 1.86 22.0 22.1
1,024 12.50 1.43 1.33 22.4 22.6
2,048 6.25 1.02 0.95 22.9 23.0
4,000 3.20 0.73 0.69 23.4 23.5
8,000 1.60 0.52 0.50 23.9 24.0
16,000 0.80 0.39 0.37 24.3 24.4
26,667 0.48 0.31 0.31 24.7 24.7
32,000 0.40 0.32 0.28 24.6 24.8
96,000 0.13 0.22 0.22 25.2 25.2
160,000 0.08 0.19 0.15 25.4 25.7
(1) High OSR values can yield varying noise results because of the limits of 24-bit quantization: 4.096V / 223 = 0.488μV / code.
Table 6-3 Sinc4 + Sinc1 Filter Noise Performance (VREF = 2.5V)
OSR DATA RATE
(kSPS)		 NOISE
(en(RMS), µVRMS)(1)		 EFFECTIVE RESOLUTION ±2.5V RANGE (Bits)
SPEED MODE 3 (fMOD =12.8MHz)

64 (32 × 2)

 200.00 6.63 19.5

128 (32 × 4)

 100.00 5.00 19.9

256 (32 × 8)

 50.00 3.71 20.4

512 (32 × 16)

 25.00 2.65 20.8

1024 (32 × 32)

 12.50 1.92 21.3

2048 (32 × 64)

 6.25 1.35 21.8

4000 (32 × 125)

 3.20 1.00 22.3

8000 (32 × 250)

 1.60 0.73 22.7

16000 (32 × 500)

 0.80 0.53 23.2

26656 (32 × 833)

 0.48 0.45 23.4

32000 (32 × 1000)

 0.40 0.43 23.5

96000 (32 × 3000)

 0.13 0.33 23.9

160000 (32 × 5000)

 0.08 0.29 24.0
SPEED MODE 2 (fMOD =6.4MHz)

64 (32 × 2)

 200.00 6.46 19.6

128 (32 × 4)

 100.00 4.94 19.9

256 (32 × 8)

 50.00 3.61 20.4

512 (32 × 16)

 25.00 2.62 20.9

1024 (32 × 32)

 12.50 1.85 21.4

2048 (32 × 64)

 6.25 1.31 21.9

4000 (32 × 125)

 3.20 0.96 22.3

8000 (32 × 250)

 1.60 0.68 22.8

16000 (32 × 500)

 0.80 0.50 23.3

26656 (32 × 833)

 0.48 0.39 23.6

32000 (32 × 1000)

 0.40 0.36 23.7

96000 (32 × 3000)

 0.13 0.22 24.4

160000 (32 × 5000)

 0.08 0.20 24.6
SPEED MODE 1 (fMOD =1.6MHz)

64 (32 × 2)

 200.00 6.37 19.6

128 (32 × 4)

 100.00 4.94 19.9

256 (32 × 8)

 50.00 3.62 20.4

512 (32 × 16)

 25.00 2.63 20.9

1024 (32 × 32)

 12.50 1.83 21.4

2048 (32 × 64)

 6.25 1.31 21.9

4000 (32 × 125)

 3.20 0.95 22.3

8000 (32 × 250)

 1.60 0.66 22.9

16000 (32 × 500)

 0.80 0.49 23.3

26656 (32 × 833)

 0.48 0.39 23.6

32000 (32 × 1000)

 0.40 0.36 23.7

96000 (32 × 3000)

 0.13 0.23 24.4

160000 (32 × 5000)

 0.08 0.20 24.6
SPEED MODE 0 (fMOD =0.8MHz)

64 (32 × 2)

 200.00 6.38 19.6

128 (32 × 4)

 100.00 4.82 20.0

256 (32 × 8)

 50.00 3.57 20.4

512 (32 × 16)

 25.00 2.54 20.9

1024 (32 × 32)

 12.50 1.85 21.4

2048 (32 × 64)

 6.25 1.33 21.8

4000 (32 × 125)

 3.20 0.94 22.3

8000 (32 × 250)

 1.60 0.67 22.8

16000 (32 × 500)

 0.80 0.47 23.3

26656 (32 × 833)

 0.48 0.36 23.7

32000 (32 × 1000)

 0.40 0.36 23.7

96000 (32 × 3000)

 0.13 0.22 24.4

160000 (32 × 5000)

 0.08 0.17 24.8
Table 6-4 Sinc4 + Sinc1 Filter Noise Performance (VREF = 4.096V)
OSR DATA RATE
(kSPS)		 NOISE
(en(RMS), µVRMS)(1)		 EFFECTIVE RESOLUTION ±4.096V RANGE (Bits)
SPEED MODE 3 (fMOD =12.8MHz)

64 (32 × 2)

 200.00 6.82 20.2

128 (32 × 4)

 100.00 5.24 20.6

256 (32 × 8)

 50.00 3.83 21.0

512 (32 × 16)

 25.00 2.73 21.5

1024 (32 × 32)

 12.50 1.96 22.0

2048 (32 × 64)

 6.25 1.43 22.4

4000 (32 × 125)

 3.20 1.04 22.9

8000 (32 × 250)

 1.60 0.74 23.4

16000 (32 × 500)

 0.80 0.57 23.8

26656 (32 × 833)

 0.48 0.46 24.1

32000 (32 × 1000)

 0.40 0.45 24.1

96000 (32 × 3000)

 0.13 0.38 24.4

160000 (32 × 5000)

 0.08 0.31 24.7
SPEED MODE 2 (fMOD =6.4MHz)

64 (32 × 2)

 200.00 6.76 20.2

128 (32 × 4)

 100.00 5.14 20.6

256 (32 × 8)

 50.00 3.73 21.1

512 (32 × 16)

 25.00 2.72 21.5

1024 (32 × 32)

 12.50 1.94 22.0

2048 (32 × 64)

 6.25 1.38 22.5

4000 (32 × 125)

 3.20 0.99 23.0

8000 (32 × 250)

 1.60 0.72 23.4

16000 (32 × 500)

 0.80 0.51 23.9

26656 (32 × 833)

 0.48 0.41 24.3

32000 (32 × 1000)

 0.40 0.39 24.3

96000 (32 × 3000)

 0.13 0.26 24.9

160000 (32 × 5000)

 0.08 0.21 25.2
SPEED MODE 1 (fMOD =1.6MHz)

64 (32 × 2)

 200.00 6.62 20.2

128 (32 × 4)

 100.00 5.13 20.6

256 (32 × 8)

 50.00 3.67 21.1

512 (32 × 16)

 25.00 2.63 21.6

1024 (32 × 32)

 12.50 1.91 22.0

2048 (32 × 64)

 6.25 1.36 22.5

4000 (32 × 125)

 3.20 0.98 23.0

8000 (32 × 250)

 1.60 0.70 23.5

16000 (32 × 500)

 0.80 0.51 23.9

26656 (32 × 833)

 0.48 0.42 24.2

32000 (32 × 1000)

 0.40 0.40 24.3

96000 (32 × 3000)

 0.13 0.27 24.9

160000 (32 × 5000)

 0.08 0.24 25.0
SPEED MODE 0 (fMOD =0.8MHz)

64 (32 × 2)

 200.00 6.63 20.2

128 (32 × 4)

 100.00 5.02 20.6

256 (32 × 8)

 50.00 3.67 21.1

512 (32 × 16)

 25.00 2.64 21.6

1024 (32 × 32)

 12.50 1.90 22.0

2048 (32 × 64)

 6.25 1.34 22.5

4000 (32 × 125)

 3.20 0.98 23.0

8000 (32 × 250)

 1.60 0.69 23.5

16000 (32 × 500)

 0.80 0.49 24.0

26656 (32 × 833)

 0.48 0.40 24.3

32000 (32 × 1000)

 0.40 0.39 24.3

96000 (32 × 3000)

 0.13 0.26 24.9

160000 (32 × 5000)

 0.08 0.21 25.2
(1) High OSR values can yield varying noise results because of the limits of 24-bit quantization: 4.096V / 223 = 0.488μV / code.

Table 6-5 and Table 6-6summarize the noise performance and effective resolution of the custom 20SPS and 25SPS filter modes with simultaneous 50Hz/60Hz rejection.

Table 6-5 20SPS Filter and 25SPS Filter Noise Performance (VREF = 2.5V)
SPEED MODE fCLK
(MHz)		 DATA RATE
(SPS)		 NOISE
(en(RMS), µVRMS)		 EFFECTIVE RESOLUTION ±2.5V RANGE (Bits)
3 12.8 20 0.24 24.3
2 6.4 20 0.16 24.9
1 1.6 20 0.29 24.0
0 0.8 20 0.36 23.7
3 12.8 25 0.26 24.2
2 6.4 25 0.17 24.8
1 1.6 25 0.30 24.0
0 0.8 25 0.40 23.6
Table 6-6 20SPS Filter and 25SPS Filter Noise Performance (VREF = 4.096V)
SPEED MODE fCLK
(MHz)		 DATA RATE
(SPS)		 NOISE
(en(RMS), µVRMS)		 EFFECTIVE RESOLUTION ±4.096V RANGE (Bits)
3 12.8 20 0.31 24.7
2 6.4 20 0.19 25.4
1 1.6 20 0.31 24.7
0 0.8 20 0.39 24.3
3 12.8 25 0.29 24.8
2 6.4 25 0.19 25.4
1 1.6 25 0.32 24.6
0 0.8 25 0.43 24.2