SLAAEH8 October   2024 AFE781H1 , AFE782H1 , AFE881H1 , AFE882H1 , DAC8740H , DAC8741H , DAC8742H

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 The 4-20mA Loop
    2. 1.2 The HART Protocol
      1. 1.2.1 Adding HART to the 4-20mA Loop
      2. 1.2.2 HART FSK
  5. 2AFE881H1 HART Modem
    1. 2.1 AFE881H1 HART Transmitter
    2. 2.2 Detailed Schematic
      1. 2.2.1 Input Protection
      2. 2.2.2 Startup Circuit
      3. 2.2.3 Voltage-to-Current Stage
      4. 2.2.4 Voltage-to-Current Calculation
      5. 2.2.5 HART Signal Transmission
      6. 2.2.6 HART Input Protection
      7. 2.2.7 Current Consumption
      8. 2.2.8 HART Transmitter Board
      9. 2.2.9 HART Protocol Stack
  6. 3HART Testing and Registration
    1. 3.1  HART History and the FieldComm Group
    2. 3.2  HART Testing Overview
      1. 3.2.1 HART Protocol Specifications
      2. 3.2.2 HART Protocol Test Specifications
      3. 3.2.3 Remote Transmitter Device Testing
    3. 3.3  HART Test Equipment
    4. 3.4  HART Physical Layer Testing
      1. 3.4.1 FSK Sinusoid Test
      2. 3.4.2 Carrier Start and Stop Time Tests
      3. 3.4.3 Carrier Start and Stop Transient Tests
      4. 3.4.4 Output Noise During Silence
      5. 3.4.5 Analog Rate of Change Test
      6. 3.4.6 Receive Impedance Test
      7. 3.4.7 Noise Sensitivity Test
      8. 3.4.8 Carrier Detect Test
    5. 3.5  Data Link Layer Tests
      1. 3.5.1 Data Link Layer Test Specifications
      2. 3.5.2 Data Link Layer Test Logs
    6. 3.6  Universal Command Tests
    7. 3.7  Common-Practice Command Tests
    8. 3.8  Device Specific Command Tests
    9. 3.9  HART Protocol Test Submission
    10. 3.10 HART Registration
  7. 4Other TI HART Modem Designs
  8. 5Summary
  9. 6Acknowledgments
  10. 7References

3.4.2 Carrier Start and Stop Time Tests

In addition to the FSK characteristics, the physical layer tests also measure the start and start times of the carrier from the transmitter. Figure 3-7 shows a figure of the carrier start and stop time test setup. When the microprocessor in the HART transmitter sends a transmission, the request-to-send (RTS) pin on the AFE881H1 is set low as a trigger to enable the modulator for the FSK. The modulator generates the sine-wave signals for the HART communication.

HART Carrier Start and Stop Time Tests Setup Figure 3-7 HART Carrier Start and Stop Time Tests Setup

When the active-low RTS pin on the AFE881H1 is set low, the modulator is enabled and the HART sinusoid appears on the MOD_OUT pin of the device. Part of the physical layer tests measure the time to enable the modulator when the RTS signal is set low, and the time to disable the modulator when the RTS signal is returned high.

In this setup, the RTS signal from the microprocessor triggers an oscilloscope to plot the enable and disable time for the HART signal. Figure 3-8 and Figure 3-9 show the required timing for the HART carrier start and stop tests.

Carrier Start Timing Figure 3-8 Carrier Start Timing
Carrier Stop Timing Figure 3-9 Carrier Stop Timing

For RTS enable, the maximum amount of time allowed to start the modulator is 5 HART bit times or 4.2ms. This is the time for the sinusoid to reach the minimum amplitude of 120mVPP. For RTS disable, the maximum carrier stop time is 2.5ms to verify that the carrier amplitude is below 80mVPP. There is a total of 5ms of allowable decay time. After this time period, the maximum noise amplitude from the HART signal is 2.2mVRMS (or about 6.16mVPP). Figure 3-10 shows the oscilloscope plot for the HART carrier start and stop timing and Table 3-2 reports the measured data.

HART Carrier Start and Stop Time Test Oscilloscope Results Figure 3-10 HART Carrier Start and Stop Time Test Oscilloscope Results
Table 3-2 FSK Sinusoid Start and Stop Time Test Results
TEST MEASURED MAXIMUM RESULT
Carrier start time 120µs 4.2ms Pass
Carrier stop time 0.4ms 2.5ms Pass
Carrier decay time 1.8ms 5.0ms Pass