SLAAEH8 October   2024 AFE781H1 , AFE782H1 , AFE881H1 , AFE882H1 , DAC8740H , DAC8741H , DAC8742H

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 The 4-20mA Loop
    2. 1.2 The HART Protocol
      1. 1.2.1 Adding HART to the 4-20mA Loop
      2. 1.2.2 HART FSK
  5. 2AFE881H1 HART Modem
    1. 2.1 AFE881H1 HART Transmitter
    2. 2.2 Detailed Schematic
      1. 2.2.1 Input Protection
      2. 2.2.2 Startup Circuit
      3. 2.2.3 Voltage-to-Current Stage
      4. 2.2.4 Voltage-to-Current Calculation
      5. 2.2.5 HART Signal Transmission
      6. 2.2.6 HART Input Protection
      7. 2.2.7 Current Consumption
      8. 2.2.8 HART Transmitter Board
      9. 2.2.9 HART Protocol Stack
  6. 3HART Testing and Registration
    1. 3.1  HART History and the FieldComm Group
    2. 3.2  HART Testing Overview
      1. 3.2.1 HART Protocol Specifications
      2. 3.2.2 HART Protocol Test Specifications
      3. 3.2.3 Remote Transmitter Device Testing
    3. 3.3  HART Test Equipment
    4. 3.4  HART Physical Layer Testing
      1. 3.4.1 FSK Sinusoid Test
      2. 3.4.2 Carrier Start and Stop Time Tests
      3. 3.4.3 Carrier Start and Stop Transient Tests
      4. 3.4.4 Output Noise During Silence
      5. 3.4.5 Analog Rate of Change Test
      6. 3.4.6 Receive Impedance Test
      7. 3.4.7 Noise Sensitivity Test
      8. 3.4.8 Carrier Detect Test
    5. 3.5  Data Link Layer Tests
      1. 3.5.1 Data Link Layer Test Specifications
      2. 3.5.2 Data Link Layer Test Logs
    6. 3.6  Universal Command Tests
    7. 3.7  Common-Practice Command Tests
    8. 3.8  Device Specific Command Tests
    9. 3.9  HART Protocol Test Submission
    10. 3.10 HART Registration
  7. 4Other TI HART Modem Designs
  8. 5Summary
  9. 6Acknowledgments
  10. 7References

2 AFE881H1 HART Modem

Here, the AFE881H1 HART modem IC is introduced. This device is used as the centerpiece for a HART-enabled transmitter. Figure 2-1 shows the AFE881H1 block diagram.

AFE881H1 Block Diagram Figure 2-1 AFE881H1 Block Diagram

The block diagram shows many of the features of the device. The AFE881H1 has a 16-bit voltage output DAC used to set the loop current and has an integrated HART modem. The DAC has user calibration that can adjust for offset and gain error. The DAC also has slew rate control that can slow DAC output transitions. The slew rate control can be used to help shape the output signal for HART testing.

The device also has an internal, 12-bit, multiplexed ADC. ADC measurements of internal nodes of the device can be monitored for programmable alarms for functional safety. An internal precision reference can be used for both the DAC and ADC.

SPI or UART communication can be used to program the device, or a combination of the two can be used for the HART protocol. The device has optional cyclic redundancy check (CRC) for error checking communications and a watchdog timer verify communication connections.

The integration of the DAC, HART modem, ADC, and other system monitor functions make the AFE881H1 a good choice as the centerpiece for a remote transmitter.