SLAAEI9A December 2023 – May 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1305 , MSPM0L1306 , MSPM0L1345
MSPM0 and STM8 both support serial peripheral interface (SPI). Overall, MSPM0 and STM8 SPI support is comparable with the difference listed in Table 4-4.
| Feature | STM8S and STM8L | MSPM0L, MSPM0L and MSPM0H |
|---|---|---|
| Operation wires | SCK, MOSI, MISO, NSS | SCLK, PICO, POCI, CSx |
| Controller or peripheral operation | Yes | Yes |
| Multiple controller capability | Yes | No |
| Data order | MSB-first or LSB-first | MSB-first or LSB-first |
| Data bit width (controller mode) | Not mentioned | 4 to 16 bit |
| Data bit width (peripheral mode) | 7 to 16 bit | |
| Maximum speed | 10MHz | 16MHz |
| Simplex transfers (unidirectional data line) | Yes | Yes |
| Hardware chip select management | Yes (1 peripheral) | Yes (4 peripherals) |
| Phase control of I/O clock | Yes | Yes |
| SPI format support | Motorola | Motorola, TI, MICROWIRE |
| Hardware CRC | Yes (STM8S) | No, MSPM0 offers SPI parity mode |
| Low power mode | Wait mode | Sleep mode |
| TX FIFO depth | 1 (buffer) | 4 |
| RX FIFO depth | 1(buffer) | 4 |
SPI Code Examples: information about SPI code examples can be found in the MSPM0 SDK examples guide.