SLAAEI9A December   2023  – May 2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0H3216-Q1 , MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1305 , MSPM0L1306 , MSPM0L1345

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of STM8 MCUs to MSPM0 MCUs
  5. 2Ecosystem And Migration
    1. 2.1 Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 IDE Supported By MSPM0
      3. 2.1.3 SysConfig
      4. 2.1.4 Debug Tools
      5. 2.1.5 LaunchPad
    2. 2.2 Migration Process
      1. 2.2.1 Step 1: Choose The Right MSPM0 MCU
      2. 2.2.2 Step 2. Set Up IDE And Quick Introduction of CCS
        1. 2.2.2.1 Set Up IDE
        2. 2.2.2.2 Quick Introduction of CCS
      3. 2.2.3 Step 3. Set Up MSPM0 SDK And Quick Introduction of MSPM0 SDK
        1. 2.2.3.1 Set Up MSPM0 SDK
        2. 2.2.3.2 Quick Introduction of SDK
      4. 2.2.4 Step 4: Software Evaluation
      5. 2.2.5 Step 5. PCB Board Design
      6. 2.2.6 Step 6. Mass Production
    3. 2.3 Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash and EEPROM Features
      2. 3.2.2 Flash and EEPROM Organization
        1. 3.2.2.1 Flash and EEPROM Regions
        2. 3.2.2.2 NONMAIN Memory of MSPM0
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power UP and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
      1. 3.4.1 Oscillators
      2. 3.4.2 Clock Signal Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Modes
      3. 3.5.3 Entering Lower-Power Modes
      4. 3.5.4 Low-Power Mode Code Examples
    6. 3.6 Interrupts and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
        1. 3.6.1.1 Interrupt Management of MSPM0
        2. 3.6.1.2 Interrupt Controller (ITC) of STM8
      2. 3.6.2 Event Handler of MSPM0
      3. 3.6.3 Event Management Comparison
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Debug Mode Comparison
      2. 3.7.2 Programming Mode Comparison
        1. 3.7.2.1 Bootstrap Loader (BSL) Programming Options
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 Interintegrated Circuit Interface (I2C)
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Voltage References (VREF)
  9. 6Summary
  10. 7References
  11. 8Revision History

3.4.2 Clock Signal Comparison

Different clock signals can be divided to source other clocks and be distributed across the multitude of peripherals.

Table 3-7 Clock Signal Comparison
Clock Description STM8L Clock STM8S Clock MSPM0L, MSPM0C and MSPM0H Clock
External digital clock input High frequency External source: up to 16MHz(1) HSE Ext: up to 24MHz(1) Lx22x and C1106: supports 32MHz
Low frequency External source: 32.768kHz(1) N/A Lx22x and C1106: supports 32KHz
High-frequency sources for main clock HSI, HSE fHSE, fHSIDIV SYSOSC
Low-frequency sources for main clock LSI, LSE fLSI LFCLK (fixed 32kHz)
Main system clock SYSCLK, fMASTER fMASTER MCLK, ULPCLK (BUSCLK)(2)
Source CPU SYSCLK, fMASTER fCPU CPUCLK
Clock for most peripheral hardware PCLK (SYSCLK), fMASTER fMASTER MCLK, ULPCLK(2)
Peripheral specific clock BEEPCLK, IWDGCLK, RTCCLK, fLSI, fHSI/2(3) N/A ADCCLK
Fixed frequency clock N/A N/A MFCLK: 4MHz, synchronized to MCLK, ULPCLK
(1) HSE crystal and LSE crystal need be switched off when external clock sources are used. STM8L001xx and STM8L101xx families don't support external digital clock input.
(2) The MCLK is the main system clock for PD1 and the ULPCLK, derived from MCLK, is the main system clock for PD0. PD1 (power domain 1) contains the CPU subsystem, memory interfaces, and high-speed peripherals. PD0 (power domain 0) contains the low-speed low-power peripherals.
(3) The fLSI of STM8L001xx and STM8L101xx families is just used to source AWU, BEEP, SWIM, IWDG. The fHSI/2 is just used to source SWIM.
Table 3-8 Peripheral Clock Sources
Peripheral STM8L, STM8S MSPM0L, MSPM0C, MSPM0H
UART/USART SYSCLK, fMASTER SYSCLK, MFCLK, LFCLK
SPI SYSCLK, fMASTER SYSCLK, MFCLK, LFCLK
I2C SYSCLK, fMASTER BUSCLK, MFCLK
ADC PCLK or PCLK/2(1), fADC (fMASTER divided by 2 to 18) ADCCLK (sourced by ULPCLK or SYSOSC)
TIMERS SYSCLK, fMASTER, fMASTER/DIV BUSCLK, MFCLK, LFCLK
COMPARATOR PCLK, fMASTER(2) BUSCLK
WATCHDOG LSI, SYSCLK, fCPU(3) LFCLK
(1) STM8L001xx and STM8L101xx microcontroller families do not have ADC.
(2) STM8S series microcontrollers do not have COMPARATOR.
(3) LSI is used to source Independent watchdog (IWDG). SYSCLK or fCPU are used to source window watchdog (WWDG).